From 42ad6de84757f52c8fe7b4c4e95b9d295ef6cd44 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 3 Mar 2020 15:40:25 +0800 Subject: [PATCH] arm64: dts: imx8mn-ddr4-evk: enable wlan/bt HIF Enable sdio HIF for wlan, and uart HIF for bluetooth to support cypress cyw43455 wireless solution. Signed-off-by: Fugang Duan Signed-off-by: Anson Huang --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index ea59a999816a..0ba61bad9d25 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -28,6 +28,21 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -365,12 +380,56 @@ status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -566,6 +625,16 @@ >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -573,6 +642,54 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 @@ -668,4 +785,11 @@ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; }; -- 2.17.1