From 3d78503e70e795ed792003cf40f4bac1597eb529 Mon Sep 17 00:00:00 2001 From: Robby Cai Date: Wed, 27 Jan 2021 21:54:32 +0800 Subject: [PATCH] MLK-23600-1 Change MIPI CSI clock to 266MHz for dual ISP cameras Set MIPI clock according to IC team. for 1 ISP camera on CSI0, MIPI CSI clock set to 500MHz for 2 ISP cameras on CSI0/CSI1, MIPI CSI clock both set to 266MHz Signed-off-by: Robby Cai Reviewed-by: Guoniu.zhou (cherry picked from commit a38f457b63fa8a0d9b4c5de39a12959c172e7e35) --- arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts index 1e3616d2084a..1bd1dc2ea82c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts @@ -86,6 +86,9 @@ &mipi_csi_0 { status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; port@0 { reg = <0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts index 6246158e0627..c08daa21c284 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts @@ -103,6 +103,9 @@ &mipi_csi_0 { status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; port@0 { endpoint { diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index b210cd3222ed..9e49db76b2f4 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1568,7 +1568,7 @@ "media_blk_csi_pclk", "media_blk_csi_aclk"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; assigned-clock-rates = <266000000>; bus-width = <4>; csi-gpr = <&mediamix_gasket1>; -- 2.17.1