From 3d64768b1b1064aed71974842a781b69ee34f8c9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 14 May 2018 13:46:58 -0300 Subject: [PATCH] MLK-18318: mx7ulp: Enable QSPI interrupt as a wakeup source on MX7ULP MX7ULP needs to have the QSPI interrupt configured as a wakeup source in the SIM_WKPU_WAKEUP_ENABLE register, otherwise the QSPI interrupts do not wakeup the CPU from idle mode leading to poor performance in Linux. The SIM_WKPU_WAKEUP_ENABLE register only exists in B0 silicon, so make sure to only write to this register in the B0 version (or greater). Signed-off-by: Fabio Estevam (cherry picked from commit 1ab33446d6843f560fb6d14c781f6417225f8f3d) (cherry picked from commit 8116f34387f8164dd72656fb8278e6df9fdf4c05) --- arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 3 +++ board/freescale/mx7ulp_evk/mx7ulp_evk.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 8f15769f1a..5d01db75fa 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -130,6 +130,9 @@ #define SIM_SOPT1_PMIC_STBY_REQ (1<<2) #define SIM_SOPT1_A7_SW_RESET (1<<0) +#define WKPU_WAKEUP_EN 0x88 +#define WKPU_QSPI_CHANNEL BIT(20) + #define IOMUXC_PCR_MUX_ALT_SHIFT (8) #define IOMUXC_PCR_MUX_ALT_MASK (0xF00) #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 4877c14465..840dbb84e0 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -65,6 +65,10 @@ int board_qspi_init(void) writel(0x03000003, (PCC1_RBASE + 0x94)); writel(0x43000003, (PCC1_RBASE + 0x94)); } + + /* Enable QSPI as a wakeup source on B0 */ + if (soc_rev() >= CHIP_REV_2_0) + setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL); return 0; } #endif -- 2.17.1