From 3b987b8df348a5ef7dd0e5808302a299377eb9b1 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Thu, 18 Feb 2016 13:36:36 -0600 Subject: [PATCH] MLK-12415: ARM: imx: imx6q: ddr3 adjust read/write latency from DCD Adjust high frequence (528M) read/write additional latency settings from target board initial configuration; Save/restore MMDC_MDMISC from DCD settings. Remove hardcodded value to issue a ZQ calibration command. Signed-off-by: Adrian Alonso Signed-off-by: Ranjani Vaidyanathan (Cherry picked from commit 1036293d72173ef9051ec23babfd4d7f13db4f58) --- arch/arm/mach-imx/busfreq_ddr3.c | 3 +++ arch/arm/mach-imx/ddr3_freq_imx6.S | 14 ++++++++------ arch/arm/mach-imx/ddr3_freq_imx6sx.S | 14 ++++++++------ 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/busfreq_ddr3.c b/arch/arm/mach-imx/busfreq_ddr3.c index 37281158fbff..d98bb26f699d 100644 --- a/arch/arm/mach-imx/busfreq_ddr3.c +++ b/arch/arm/mach-imx/busfreq_ddr3.c @@ -137,6 +137,7 @@ unsigned long ddr3_dll_mx6sx[][2] = { {0x1C, 0x05208030}, {0x1C, 0x04008040}, {0x818, 0x0}, + {0x18, 0x0}, }; unsigned long ddr3_calibration_mx6sx[][2] = { @@ -166,6 +167,7 @@ unsigned long ddr3_dll_mx6q[][2] = { {0x1C, 0x08408030}, {0x1C, 0x08408038}, {0x818, 0x0}, + {0x18, 0x0}, }; unsigned long ddr3_calibration[][2] = { @@ -198,6 +200,7 @@ unsigned long ddr3_dll_mx6dl[][2] = { {0x1C, 0x07208030}, {0x1C, 0x07208038}, {0x818, 0x0}, + {0x18, 0x0}, }; unsigned long iomux_offsets_mx6dl[][2] = { diff --git a/arch/arm/mach-imx/ddr3_freq_imx6.S b/arch/arm/mach-imx/ddr3_freq_imx6.S index ddac7f1284bf..2a12669a3bef 100644 --- a/arch/arm/mach-imx/ddr3_freq_imx6.S +++ b/arch/arm/mach-imx/ddr3_freq_imx6.S @@ -659,7 +659,11 @@ cont_1: orr r0, r0, #0x4 str r0, [r5, #MMDC0_MDCF1] - ldr r0, =0x00011680 + ldr r0, [r5, #MMDC0_MDMISC] + bic r0, r0, #(0x3 << 16) /* walat = 0x1 */ + orr r0, r0, #(0x1 << 16) + bic r0, r0, #(0x7 << 6) /* ralat = 0x2 */ + orr r0, r0, #(0x2 << 6) str r0, [r5, #MMDC0_MDMISC] /* enable dqs pull down in the IOMUX. */ @@ -790,7 +794,9 @@ poll_dvfs_clear_2: cmp r9, #0 beq update_calibration_only - ldr r0, =0xa1390003 + /* issue zq calibration command */ + ldr r0, [r5, #MMDC0_MPZQHWCTRL] + orr r0, r0, #0x3 str r0, [r5, #MMDC0_MPZQHWCTRL] ldr r2, =MMDC1_MPZQHWCTRL str r0, [r5, r2] @@ -847,10 +853,6 @@ update_iomux1: str r3, [r5, r0] add r8, r8, #8 - /* update MISC register: WALAT, RALAT */ - ldr r0, =0x00001740 - str r0, [r5, #MMDC0_MDMISC] - /* configure ddr devices to dll on, odt. */ ldr r0, =0x00048031 str r0, [r5, #MMDC0_MDSCR] diff --git a/arch/arm/mach-imx/ddr3_freq_imx6sx.S b/arch/arm/mach-imx/ddr3_freq_imx6sx.S index 4dc89b9c3744..9846c05f4541 100644 --- a/arch/arm/mach-imx/ddr3_freq_imx6sx.S +++ b/arch/arm/mach-imx/ddr3_freq_imx6sx.S @@ -401,7 +401,11 @@ poll_dvfs_clear_1: orr r8, r8, #0x4 str r8, [r4, #MMDC0_MDCF1] - ldr r8, =0x00091680 + ldr r8, [r4, #MMDC0_MDMISC] + bic r8, r8, #(0x3 << 16) /* walat = 0x1 */ + orr r8, r8, #(0x1 << 16) + bic r8, r8, #(0x7 << 6) /* ralat = 0x2 */ + orr r8, r8, #(0x2 << 6) str r8, [r4, #MMDC0_MDMISC] /* enable dqs pull down in the IOMUX. */ @@ -506,7 +510,9 @@ poll_dvfs_clear_2: cmp r2, #0 beq update_calibration_only - ldr r8, =0xa5390003 + /* issue zq calibration command */ + ldr r8, [r4, #MMDC0_MPZQHWCTRL] + orr r8, r8, #0x3 str r8, [r4, #MMDC0_MPZQHWCTRL] /* enable DQS gating. */ @@ -551,10 +557,6 @@ update_iomux1: str r11, [r4, r10] add r1, r1, #8 - /* update MISC register: WALAT, RALAT */ - ldr r8, =0x00081740 - str r8, [r4, #MMDC0_MDMISC] - /* configure ddr devices to dll on, odt. */ ldr r8, =0x00028031 str r8, [r4, #MMDC0_MDSCR] -- 2.17.1