From 3ab19a340b46d64e5735b339ae7fb3344523955e Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Fri, 29 Nov 2019 17:22:29 +0800 Subject: [PATCH] LF-257-02 dts: imx6ull: change the usdhc root clock to 396MHz Due to the errata ERR010450 limit, this patch change the imx6ull usdhc root clock to 132MHz in soc related dts file, remove all the root clock setting in board dts file, after this patch, SDR104/HS200 work at 132MHz, DDR50/DDR52 work at 33MHz. (merged from commit: 1a3160ae69f725237752f65ee7bd47f5db4cfc1d) Reviewed-by: Haibo Chen Signed-off-by: Haibo Chen Signed-off-by: Arulpandiyan Vadivel Signed-off-by: Srikanth Krishnakar Signed-off-by: Fugang Duan --- arch/arm/boot/dts/imx6ull.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index c986bbaf3fbc..b17eef9d4888 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -46,10 +46,16 @@ &usdhc1 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; &usdhc2 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; / { -- 2.17.1