From 393d111e71f67971e876f13d53b492f9616889e1 Mon Sep 17 00:00:00 2001 From: Ella Feng Date: Wed, 25 Mar 2020 18:33:34 +0800 Subject: [PATCH] MGS-5584 arm64: imx8mn.dtsi: GPU reg format should align with soc0. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit GPU node is now within soc0 node, reg format need follow “#address-cells = <1>;#size-cells = <1>;” as soc0. Signed-off-by: Ella Feng --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 633cdcbf9f27..d06b251632f5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1295,9 +1295,9 @@ gpu: gpu@38000000 { compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu"; - reg = <0x0 0x38000000 0x0 0x40000>, - <0x0 0x40000000 0x0 0x80000000>, - <0x0 0x0 0x0 0x8000000>; + reg = <0x38000000 0x40000>, + <0x40000000 0x80000000>, + <0x0 0x8000000>; reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; interrupts = ; interrupt-names = "irq_3d"; -- 2.17.1