From 37149300cf9de21eff98e59357fa74cc6f50badd Mon Sep 17 00:00:00 2001 From: Laurentiu Palcu Date: Tue, 6 Mar 2018 13:56:55 +0200 Subject: [PATCH] MLK-17645: drm: imx: dcss: fix DTRC start issue The following commit: af01350 - MLK-17634-18: drm: imx: dcss: optimize context loading and DDR bus load introduced a regression. During my attempts to fix various green screen issues, I modified the DTRC start routine by enabling the other register bank, not the current one. Unfortunately, this was committed by mistake... Signed-off-by: Laurentiu Palcu --- drivers/gpu/imx/dcss/dcss-dtrc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/imx/dcss/dcss-dtrc.c b/drivers/gpu/imx/dcss/dcss-dtrc.c index ea485cb4f81d..d7e1448e7ff0 100644 --- a/drivers/gpu/imx/dcss/dcss-dtrc.c +++ b/drivers/gpu/imx/dcss/dcss-dtrc.c @@ -484,9 +484,9 @@ void dcss_dtrc_enable(struct dcss_soc *dcss, int ch_num, bool enable) fdctl |= COMPRESSION_DIS; dcss_dtrc_write(dtrc, ch_num, fdctl, - curr_frame * DTRC_F1_OFS + DCSS_DTRC_DCTL); - dcss_dtrc_write(dtrc, ch_num, fdctl | (enable ? CONFIG_READY : 0), (curr_frame ^ 1) * DTRC_F1_OFS + DCSS_DTRC_DCTL); + dcss_dtrc_write(dtrc, ch_num, fdctl | (enable ? CONFIG_READY : 0), + curr_frame * DTRC_F1_OFS + DCSS_DTRC_DCTL); ch->curr_frame = curr_frame; ch->dctl = fdctl; -- 2.17.1