From 33b36b6c0203cf52961414dccf6e771d2adda7fe Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Thu, 13 Jul 2017 10:20:15 +0800 Subject: [PATCH] MLK-16136-1 clk: imx: imx8mq: define DCSS root clocks. Define three root clocks for DCSS module: .IMX8MQ_CLK_DISP_AXI_ROOT .IMX8MQ_CLK_DISP_APB_ROOT .IMX8MQ_CLK_DISP_RTRM_ROOT These root clocks share one clock gate along with 'IMX8MQ_CLK_DISP_ROOT' clock. So change its type to be shared gate clock too. Signed-off-by: Fancy Fang --- drivers/clk/imx/clk-imx8mq.c | 6 +++++- include/dt-bindings/clock/imx8mq-clock.h | 7 ++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 9075916ff660..38cafa6f98f6 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -28,6 +28,7 @@ static u32 share_count_sai3; static u32 share_count_sai4; static u32 share_count_sai5; static u32 share_count_sai6; +static u32 share_count_dcss; static struct clk *clks[IMX8MQ_CLK_END]; @@ -797,7 +798,10 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node) clks[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_gate4("vpu_g1_root_clk", "vpu_g1_div", base + 0x4560, 0); clks[IMX8MQ_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0); clks[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2_div", base + 0x45a0, 0); - clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate4("disp_root_clk", "disp_dc8000_div", base + 0x45d0, 0); + clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000_div", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi_div", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb_div", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm_div", base + 0x45d0, 0, &share_count_dcss); clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0); clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus_div", base + 0x4630, 0); clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core_div", base + 0x4650, 0); diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 11dcafcfde81..1c431d01cc30 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -608,5 +608,10 @@ #define IMX8MQ_VIDEO2_PLL2_OUT 474 #define IMX8MQ_CLK_TMU_ROOT 475 -#define IMX8MQ_CLK_END 476 +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 476 +#define IMX8MQ_CLK_DISP_APB_ROOT 477 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 478 + +#define IMX8MQ_CLK_END 479 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ -- 2.17.1