From 3332ea64bc70cbe415028026f5e2896856749a9c Mon Sep 17 00:00:00 2001 From: Silvano di Ninno Date: Wed, 1 Apr 2020 13:43:30 +0200 Subject: [PATCH] TEE-520 core: imx: Set TZASC region 0 to non-sec As it is done in ATF for i.MX 8 SoC. Enable and set region 0 attribute to be allow secure and non-secure transaction. Signed-off-by: Silvano di Ninno Reviewed-by: Ye Li (cherry picked from commit b81e528dd232b8c2f4d10e89c6bf20c65263b14e) (cherry picked from commit 7c8809d90ed336550906e3108fe8dc99c6bea3e7) --- arch/arm/include/asm/arch-mx7/imx-regs.h | 2 +- arch/arm/mach-imx/misc.c | 14 ++++++++++++++ arch/arm/mach-imx/mx6/soc.c | 13 ------------- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index a539e2941e..52bfc12e5d 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -143,7 +143,7 @@ #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) -#define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) +#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index 2de7444002..3fee7ed90e 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -111,11 +111,25 @@ void board_lmb_reserve(struct lmb *lmb) } } +static void configure_tzc380(void) +{ +#if defined (IP2APB_TZASC1_BASE_ADDR) + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + if (iomux->gpr[9] & 0x1) + writel(0xf0000000, IP2APB_TZASC1_BASE_ADDR + 0x108); +#endif +#if defined (IP2APB_TZASC2_BASE_ADDR) + if (iomux->gpr[9] & 0x2) + writel(0xf0000000, IP2APB_TZASC2_BASE_ADDR + 0x108); +#endif +} + void imx_sec_init(void) { #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) caam_open(); #endif + configure_tzc380(); } static void set_dt_val(void *data, uint32_t cell_size, uint64_t val) diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e4431c8f70..f760e23c68 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -642,19 +642,6 @@ int arch_cpu_init(void) 0x3, MX6UL_SNVS_LP_BASE_ADDR); } - if (is_mx6ull() || is_mx6ul()) { - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - if (iomux->gpr[9] & 0x1) { - /* When trust zone is enabled, - * set Region 0 attribute to allow secure and non-secure read/write permission - * Because PL301 hard code to non-secure for some masters on m_3/4/5 ports. - * Like LCDIF, PXP, CSI can't work with secure memory. - */ - - writel(0xf0000000, IP2APB_TZASC1_BASE_ADDR + 0x108); - } - } - /* Set perclk to source from OSC 24MHz */ if (has_err007805()) setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); -- 2.17.1