From 2ee2fa6d2cc0f3328d26b47f3973b80bc8074fcf Mon Sep 17 00:00:00 2001 From: Oliver Brown Date: Wed, 7 Mar 2018 13:27:47 -0600 Subject: [PATCH] MLK-17729: ARM64: dts: Add power domains for display resources Some resources are being enabled without the associated resource being powered up. Signed-off-by: Oliver Brown --- arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 33 +++++++++++++++-- .../arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 35 ++++++++++++++++--- include/dt-bindings/soc/imx8_pd.h | 4 +++ 3 files changed, 65 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index 0fe322ac5615..230de5fd804c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -180,6 +180,20 @@ #address-cells = <1>; #size-cells = <0>; + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; + pd_mipi0: PD_MIPI_0_DSI { reg = ; #power-domain-cells = <0>; @@ -248,6 +262,21 @@ #power-domain-cells = <0>; #address-cells = <1>; #size-cells = <0>; + + pd_dc1_pll0: PD_DC_1_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc1_pll1: PD_DC_1_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1_pll0>; + }; + }; + pd_mipi1: PD_MIPI_1_DSI { reg = ; #power-domain-cells = <0>; @@ -1409,7 +1438,7 @@ <&clk IMX8QM_DC0_DISP1_SEL>; assigned-clock-parents = <&clk IMX8QM_DC0_PLL0_CLK>, <&clk IMX8QM_DC0_PLL1_CLK>; - power-domains = <&pd_dc0>; + power-domains = <&pd_dc0_pll1>; fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, <&dpr1_channel3>, <&dpr2_channel1>, <&dpr2_channel2>, <&dpr2_channel3>; @@ -1873,7 +1902,7 @@ <&clk IMX8QM_DC1_DISP1_SEL>; assigned-clock-parents = <&clk IMX8QM_DC1_PLL0_CLK>, <&clk IMX8QM_DC1_PLL1_CLK>; - power-domains = <&pd_dc1>; + power-domains = <&pd_dc1_pll1>; fsl,dpr-channels = <&dpr3_channel1>, <&dpr3_channel2>, <&dpr3_channel3>, <&dpr4_channel1>, <&dpr4_channel2>, <&dpr4_channel3>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index e47067bd0581..1bc48cf79399 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -719,6 +719,19 @@ #address-cells = <1>; #size-cells = <0>; + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; pd_mipi_dsi0: PD_MIPI_0_DSI { reg = ; #power-domain-cells = <0>; @@ -726,6 +739,12 @@ #address-cells = <1>; #size-cells = <0>; + pd_mipi_dsi_0_lvds: PD_LVDS0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 { reg = ; #power-domain-cells = <0>; @@ -750,6 +769,12 @@ #address-cells = <1>; #size-cells = <0>; + pd_mipi_dsi_1_lvds: PD_LVDS1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 { reg = ; #power-domain-cells = <0>; @@ -1158,7 +1183,7 @@ <&clk IMX8QXP_DC0_DISP0_CLK>, <&clk IMX8QXP_DC0_DISP1_CLK>; clock-names = "pll0", "pll1", "disp0", "disp1"; - power-domains = <&pd_dc0>; + power-domains = <&pd_dc0_pll1>; fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, <&dpr1_channel3>, <&dpr2_channel1>, <&dpr2_channel2>, <&dpr2_channel3>; @@ -1294,7 +1319,7 @@ #phy-cells = <0>; clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>; clock-names = "phy"; - power-domains = <&pd_mipi_dsi0>; + power-domains = <&pd_mipi_dsi_0_lvds>; status = "disabled"; }; @@ -1305,7 +1330,7 @@ clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; clock-names = "pixel", "bypass"; - power-domains = <&pd_mipi_dsi0>; + power-domains = <&pd_mipi_dsi_0_lvds>; gpr = <&lvds_region1>; status = "disabled"; @@ -1455,7 +1480,7 @@ #phy-cells = <0>; clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>; clock-names = "phy"; - power-domains = <&pd_mipi_dsi1>; + power-domains = <&pd_mipi_dsi_1_lvds>; status = "disabled"; }; @@ -1466,7 +1491,7 @@ clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; clock-names = "pixel", "bypass"; - power-domains = <&pd_mipi_dsi1>; + power-domains = <&pd_mipi_dsi_1_lvds>; gpr = <&lvds_region2>; status = "disabled"; diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h index 369a18dcf1e3..34fd2e9acb6f 100644 --- a/include/dt-bindings/soc/imx8_pd.h +++ b/include/dt-bindings/soc/imx8_pd.h @@ -22,6 +22,8 @@ * never be changed or removed (only added to at the end of the list). */ #define PD_DC_0 dc0_power_domain +#define PD_DC_0_PLL_0 dc0_pll0 +#define PD_DC_0_PLL_1 dc0_pll1 #define PD_LVDS0 lvds0_power_domain #define PD_LVDS0_I2C0 lvds0_i2c0 #define PD_LVDS0_I2C1 lvds0_i2c1 @@ -29,6 +31,8 @@ #define PD_LVDS0_PWM lvds0_pwm #define PD_LVDS0_GPIO lvds0_gpio #define PD_DC_1 dc1_power_domain +#define PD_DC_1_PLL_0 dc1_pll0 +#define PD_DC_1_PLL_1 dc1_pll1 #define PD_LVDS1 lvds1_power_domain #define PD_LVDS1_I2C0 lvds1_i2c0 #define PD_LVDS1_I2C1 lvds1_i2c1 -- 2.17.1