From 2d0bd13ec191791fd467f942bc8f558cd67c7fac Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 27 Jul 2015 19:17:06 +0800 Subject: [PATCH] MLK-11281-15 ARM: imx: add gpcv2 save/restore for lpsr Redo necessary gpcv2 initialization after resume from LPSR mode, as its state is lost in lpsr mode. Signed-off-by: Anson Huang --- arch/arm/mach-imx/gpcv2.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index 2d5ff324c40d..af1a57afb356 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -500,7 +500,31 @@ void imx_gpcv2_pre_suspend(bool arm_power_off) void imx_gpcv2_post_resume(void) { void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; - int i; + int i, val; + + /* only external IRQs to wake up LPM and core 0/1 */ + val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP; + writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC); + /* mask m4 dsm trigger */ + writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) | + BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4); + /* set mega/fast mix in A7 domain */ + writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_MAPPING); + /* set SCU timing */ + writel_relaxed((0x59 << 10) | 0x5B | (0x51 << 20), + gpc_base + GPC_PGC_SCU_TIMING); + + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); for (i = 0; i < IMR_NUM; i++) writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4); -- 2.17.1