From 2cb363b5473c9cc90aeb52d1c17a07ee21ae9d54 Mon Sep 17 00:00:00 2001 From: eduard Date: Wed, 4 Aug 2021 00:50:56 +0200 Subject: [PATCH] meta-somdevices: Created imx8mm-somdevices-c0p1 machine --- COPYING.MIT | 17 + README | 41 + conf/layer.conf | 17 + conf/machine/imx8mm-somdevices-c0p1.conf | 40 + ...mdevices-imx8mm-lpddr4-configuration.patch | 186 +++ .../0002-change-memory-size-2G-to-1G.patch | 49 + .../files/0003-Change-usd-cd-gpio.patch | 35 + .../files/0004-Change-uart2-pinmux.patch | 27 + ...005-Change-uart2-PAD-on-imx8mm_evk.c.patch | 27 + recipes-bsp/u-boot/u-boot-imx_%.bbappend | 9 + recipes-example/example/example_0.1.bb | 13 + ...dd-SomDevices-Smarc-C0P1-to-Makefile.patch | 24 + .../0002-arm64-Add-sn65dsi83-4-support.patch | 1040 +++++++++++++++ ...64-Not-to-show-warning-CAN-interface.patch | 27 + .../linux/files/imx8mm-somdevices-c0p1.dts | 156 +++ .../linux/files/imx8mm-somdevices-c0p1.dtsi | 1160 +++++++++++++++++ recipes-kernel/linux/linux-imx_%.bbappend | 19 + 17 files changed, 2887 insertions(+) create mode 100644 COPYING.MIT create mode 100644 README create mode 100644 conf/layer.conf create mode 100644 conf/machine/imx8mm-somdevices-c0p1.conf create mode 100644 recipes-bsp/u-boot/files/0001-imx-Add-somdevices-imx8mm-lpddr4-configuration.patch create mode 100644 recipes-bsp/u-boot/files/0002-change-memory-size-2G-to-1G.patch create mode 100644 recipes-bsp/u-boot/files/0003-Change-usd-cd-gpio.patch create mode 100644 recipes-bsp/u-boot/files/0004-Change-uart2-pinmux.patch create mode 100644 recipes-bsp/u-boot/files/0005-Change-uart2-PAD-on-imx8mm_evk.c.patch create mode 100644 recipes-bsp/u-boot/u-boot-imx_%.bbappend create mode 100644 recipes-example/example/example_0.1.bb create mode 100644 recipes-kernel/linux/files/0001-arm64-Add-SomDevices-Smarc-C0P1-to-Makefile.patch create mode 100644 recipes-kernel/linux/files/0002-arm64-Add-sn65dsi83-4-support.patch create mode 100644 recipes-kernel/linux/files/0003-arm64-Not-to-show-warning-CAN-interface.patch create mode 100644 recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dts create mode 100644 recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dtsi create mode 100644 recipes-kernel/linux/linux-imx_%.bbappend diff --git a/COPYING.MIT b/COPYING.MIT new file mode 100644 index 0000000..fb950dc --- /dev/null +++ b/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/README b/README new file mode 100644 index 0000000..526746f --- /dev/null +++ b/README @@ -0,0 +1,41 @@ +This README file contains information on the contents of the meta-somdevices layer. + +Please see the corresponding sections below for details. + +Dependencies +============ + + URI: + branch: + + URI: + branch: + + . + . + . + +Patches +======= + +Please submit any patches against the meta-somdevices layer to the xxxx mailing list (xxxx@zzzz.org) +and cc: the maintainer: + +Maintainer: XXX YYYYYY + +Table of Contents +================= + + I. Adding the meta-somdevices layer to your build + II. Misc + + +I. Adding the meta-somdevices layer to your build +================================================= + +Run 'bitbake-layers add-layer meta-somdevices' + +II. Misc +======== + +--- replace with specific information about the meta-somdevices layer --- diff --git a/conf/layer.conf b/conf/layer.conf new file mode 100644 index 0000000..3689f3b --- /dev/null +++ b/conf/layer.conf @@ -0,0 +1,17 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have a recipes directory, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "somdevices" +BBFILE_PATTERN_somdevices = "^${LAYERDIR}/" +BBFILE_PRIORITY_somdevices = "9" +LAYERSERIES_COMPAT_somdevices = "hardknott" + +UBOOT_DTB_NAME_imx8mm-somdevices-c0p1 = "imx8mm-evk.dtb" +KERNEL_DEVICETREE_imx8mm-somdevices-c0p1 = "freescale/imx8mm-somdevices-c0p1.dtb" + +# Avoid multiple runtime providers for u-boot-default-env +PREFERRED_RPROVIDER_u-boot-default-env ??= "${IMX_DEFAULT_BOOTLOADER}" diff --git a/conf/machine/imx8mm-somdevices-c0p1.conf b/conf/machine/imx8mm-somdevices-c0p1.conf new file mode 100644 index 0000000..257984a --- /dev/null +++ b/conf/machine/imx8mm-somdevices-c0p1.conf @@ -0,0 +1,40 @@ +#@TYPE: Machine +#@NAME: NXP i.MX8MM LPDDR4 SomDevices SMARC +#@SOC: i.MX8MM +#@DESCRIPTION: Machine configuration for SomDevices SMARC imx8mm +#@MAINTAINER: SomDevices + +MACHINEOVERRIDES =. "mx8:mx8m:mx8mm:" + +require conf/machine/include/imx-base.inc +require conf/machine/include/tune-cortexa53.inc + +MACHINE_FEATURES += " pci wifi bluetooth optee" +KERNEL_DEVICETREE = "freescale/imx8mm-somdevices-c0p1.dtb" + +UBOOT_CONFIG ??= "sd" +UBOOT_CONFIG[sd] = "imx8mm_evk_config,sdcard" +UBOOT_CONFIG[fspi] = "imx8mm_evk_fspi_defconfig" +UBOOT_CONFIG[mfgtool] = "imx8mm_evk_config" +SPL_BINARY = "spl/u-boot-spl.bin" + +# Set DDR FIRMWARE +DDR_FIRMWARE_NAME = "lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_dmem.bin" + +# Set u-boot DTB +UBOOT_DTB_NAME = "fsl-imx8mm-evk.dtb" + +# Set imx-mkimage boot target +IMXBOOT_TARGETS = "${@bb.utils.contains('UBOOT_CONFIG', 'fspi', 'flash_evk_flexspi', 'flash_evk', d)}" + +# Set Serial console +SERIAL_CONSOLES = "115200;ttymxc1" + +IMAGE_BOOTLOADER = "imx-boot" + +LOADADDR = "" +UBOOT_SUFFIX = "bin" +UBOOT_MAKE_TARGET = "" +IMX_BOOT_SEEK = "33" + +OPTEE_BIN_EXT = "8mm" diff --git a/recipes-bsp/u-boot/files/0001-imx-Add-somdevices-imx8mm-lpddr4-configuration.patch b/recipes-bsp/u-boot/files/0001-imx-Add-somdevices-imx8mm-lpddr4-configuration.patch new file mode 100644 index 0000000..1deb57e --- /dev/null +++ b/recipes-bsp/u-boot/files/0001-imx-Add-somdevices-imx8mm-lpddr4-configuration.patch @@ -0,0 +1,186 @@ +From 5b452d3f172774859a273db5535587bcdc0a6760 Mon Sep 17 00:00:00 2001 +From: Josep Orga +Date: Wed, 30 Jun 2021 19:52:08 +0200 +Subject: [PATCH] imx: Add somdevices imx8mm lpddr4 configuration. + +Signed-off-by: Josep Orga +--- + board/freescale/imx8mm_evk/lpddr4_timing.c | 78 +++++++++++----------- + 1 file changed, 39 insertions(+), 39 deletions(-) + +diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c +index 3495b9c931..348b0b8e8d 100644 +--- a/board/freescale/imx8mm_evk/lpddr4_timing.c ++++ b/board/freescale/imx8mm_evk/lpddr4_timing.c +@@ -1,22 +1,27 @@ + /* +- * Copyright 2018-2019 NXP ++ * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool ++ * ++ * Align with uboot version: ++ * imx_v2019.04_5.4.x and above version ++ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: ++ * please replace #include with #include + */ + + #include + #include + + struct dram_cfg_param ddr_ddrc_cfg[] = { +- /* Initialize DDRC registers */ ++ /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, +- { 0x3d400020, 0x223 }, +- { 0x3d400024, 0x16e3600 }, +- { 0x3d400064, 0x5b00d2 }, ++ { 0x3d400020, 0x203 }, ++ { 0x3d400024, 0x3a980 }, ++ { 0x3d400064, 0x5b0087 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, +@@ -32,7 +37,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, +- { 0x3d400138, 0xd8 }, ++ { 0x3d400138, 0x8d }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, +@@ -45,7 +50,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, +- { 0x3d4001c4, 0x0 }, ++ { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, +@@ -53,9 +58,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, +- { 0x3d400218, 0x7070707 }, +- +- /* performance setting */ ++ { 0x3d400218, 0xf070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, +@@ -67,12 +70,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, +- +- /* P1: 400mts */ +- { 0x3d402020, 0x21 }, +- { 0x3d402024, 0x30d400 }, ++ { 0x3d402020, 0x1 }, ++ { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, +- { 0x3d402064, 0xc001c }, ++ { 0x3d402064, 0xc0012 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, +@@ -87,18 +88,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, +- { 0x3d402138, 0x1d }, ++ { 0x3d402138, 0x13 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, +- +- /* p2: 100mts */ +- { 0x3d403020, 0x21 }, +- { 0x3d403024, 0xc3500 }, ++ { 0x3d4020f4, 0xc99 }, ++ { 0x3d403020, 0x1 }, ++ { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, +- { 0x3d403064, 0x30007 }, ++ { 0x3d403064, 0x30005 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, +@@ -113,14 +113,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, +- { 0x3d403138, 0x8 }, ++ { 0x3d403138, 0x5 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, +- +- /* default boot point */ ++ { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, + }; + +@@ -136,20 +135,20 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, +- { 0x110a2, 0x3 }, +- { 0x110a3, 0x4 }, +- { 0x110a4, 0x5 }, +- { 0x110a5, 0x2 }, +- { 0x110a6, 0x7 }, +- { 0x110a7, 0x6 }, ++ { 0x110a2, 0x2 }, ++ { 0x110a3, 0x3 }, ++ { 0x110a4, 0x4 }, ++ { 0x110a5, 0x5 }, ++ { 0x110a6, 0x6 }, ++ { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, +- { 0x120a1, 0x1 }, +- { 0x120a2, 0x3 }, +- { 0x120a3, 0x2 }, +- { 0x120a4, 0x5 }, +- { 0x120a5, 0x4 }, +- { 0x120a6, 0x7 }, +- { 0x120a7, 0x6 }, ++ { 0x120a1, 0x6 }, ++ { 0x120a2, 0x7 }, ++ { 0x120a3, 0x5 }, ++ { 0x120a4, 0x4 }, ++ { 0x120a5, 0x2 }, ++ { 0x120a6, 0x3 }, ++ { 0x120a7, 0x1 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, +@@ -208,8 +207,8 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, +- { 0x120056, 0xa }, +- { 0x220056, 0xa }, ++ { 0x120056, 0x3 }, ++ { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, +@@ -1850,3 +1849,4 @@ struct dram_timing_info dram_timing = { + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, + }; ++ +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/files/0002-change-memory-size-2G-to-1G.patch b/recipes-bsp/u-boot/files/0002-change-memory-size-2G-to-1G.patch new file mode 100644 index 0000000..1df8182 --- /dev/null +++ b/recipes-bsp/u-boot/files/0002-change-memory-size-2G-to-1G.patch @@ -0,0 +1,49 @@ +From eb818b6d998dbae07ff690286bc6d9a127567994 Mon Sep 17 00:00:00 2001 +From: josep orga +Date: Thu, 1 Jul 2021 13:13:15 +0000 +Subject: [PATCH] change memory size 2G to 1G + +--- + arch/arm/dts/imx8mm-evk.dtsi | 2 +- + include/configs/imx8mm_evk.h | 5 +++-- + 2 files changed, 4 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi +index 097fdce9e1..a3c8be9048 100644 +--- a/arch/arm/dts/imx8mm-evk.dtsi ++++ b/arch/arm/dts/imx8mm-evk.dtsi +@@ -15,7 +15,7 @@ + + memory@40000000 { + device_type = "memory"; +- reg = <0x0 0x40000000 0 0x80000000>; ++ reg = <0x0 0x40000000 0 0x40000000>; + }; + + leds { +diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h +index f5bcdd245e..8a8f171408 100644 +--- a/include/configs/imx8mm_evk.h ++++ b/include/configs/imx8mm_evk.h +@@ -204,7 +204,7 @@ + #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 ++#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 + #define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + #define CONFIG_SYS_INIT_SP_ADDR \ +@@ -224,7 +224,8 @@ + + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 +-#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ ++#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ ++#define CONFIG_NR_DRAM_BANKS 1 + + #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +-- +2.25.1 + diff --git a/recipes-bsp/u-boot/files/0003-Change-usd-cd-gpio.patch b/recipes-bsp/u-boot/files/0003-Change-usd-cd-gpio.patch new file mode 100644 index 0000000..f9fd0df --- /dev/null +++ b/recipes-bsp/u-boot/files/0003-Change-usd-cd-gpio.patch @@ -0,0 +1,35 @@ +From 1acd222f1cca4e34d34ec9399998cd85fbb5176f Mon Sep 17 00:00:00 2001 +From: eduard gavin +Date: Sun, 4 Jul 2021 10:59:39 +0000 +Subject: [PATCH] Change usd-cd gpio + +--- + arch/arm/dts/imx8mm-evk.dtsi | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi +index a3c8be9048..d96275c7ff 100644 +--- a/arch/arm/dts/imx8mm-evk.dtsi ++++ b/arch/arm/dts/imx8mm-evk.dtsi +@@ -403,7 +403,7 @@ + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +- cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; ++ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +@@ -573,7 +573,8 @@ + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < +- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 ++// MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 ++ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + +-- +2.25.1 + diff --git a/recipes-bsp/u-boot/files/0004-Change-uart2-pinmux.patch b/recipes-bsp/u-boot/files/0004-Change-uart2-pinmux.patch new file mode 100644 index 0000000..5884826 --- /dev/null +++ b/recipes-bsp/u-boot/files/0004-Change-uart2-pinmux.patch @@ -0,0 +1,27 @@ +From f068f583a25cc552aa9ece3b378a49858f13e7c1 Mon Sep 17 00:00:00 2001 +From: eduard gavin +Date: Wed, 7 Jul 2021 20:42:39 +0000 +Subject: [PATCH] Change uart2 pinmux + +--- + arch/arm/dts/imx8mm-evk.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi +index d96275c7ff..952173f815 100644 +--- a/arch/arm/dts/imx8mm-evk.dtsi ++++ b/arch/arm/dts/imx8mm-evk.dtsi +@@ -566,8 +566,8 @@ + + pinctrl_uart2: uart2grp { + fsl,pins = < +- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 +- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 ++ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 ++ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + >; + }; + +-- +2.25.1 + diff --git a/recipes-bsp/u-boot/files/0005-Change-uart2-PAD-on-imx8mm_evk.c.patch b/recipes-bsp/u-boot/files/0005-Change-uart2-PAD-on-imx8mm_evk.c.patch new file mode 100644 index 0000000..7460669 --- /dev/null +++ b/recipes-bsp/u-boot/files/0005-Change-uart2-PAD-on-imx8mm_evk.c.patch @@ -0,0 +1,27 @@ +From a2d880ece8c0fc196c6fd1bb0e11f578641a2fc4 Mon Sep 17 00:00:00 2001 +From: eduard gavin +Date: Wed, 7 Jul 2021 21:41:17 +0000 +Subject: [PATCH] Change UART2 PAD on imx8mm_evk.c + +--- + board/freescale/imx8mm_evk/imx8mm_evk.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c +index eaa2c6b7f1..1ff74f43ae 100644 +--- a/board/freescale/imx8mm_evk/imx8mm_evk.c ++++ b/board/freescale/imx8mm_evk/imx8mm_evk.c +@@ -28,8 +28,8 @@ DECLARE_GLOBAL_DATA_PTR; + #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + + static iomux_v3_cfg_t const uart_pads[] = { +- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), ++ IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), ++ IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + }; + + static iomux_v3_cfg_t const wdog_pads[] = { +-- +2.25.1 + diff --git a/recipes-bsp/u-boot/u-boot-imx_%.bbappend b/recipes-bsp/u-boot/u-boot-imx_%.bbappend new file mode 100644 index 0000000..2109164 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-imx_%.bbappend @@ -0,0 +1,9 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +SRC_URI_append_imx8mm-somdevices-c0p1 += " \ + file://0001-imx-Add-somdevices-imx8mm-lpddr4-configuration.patch \ + file://0002-change-memory-size-2G-to-1G.patch \ + file://0003-Change-usd-cd-gpio.patch \ + file://0004-Change-uart2-pinmux.patch \ + file://0005-Change-uart2-PAD-on-imx8mm_evk.c.patch \ +" diff --git a/recipes-example/example/example_0.1.bb b/recipes-example/example/example_0.1.bb new file mode 100644 index 0000000..facaae3 --- /dev/null +++ b/recipes-example/example/example_0.1.bb @@ -0,0 +1,13 @@ +SUMMARY = "bitbake-layers recipe" +DESCRIPTION = "Recipe created by bitbake-layers" +LICENSE = "MIT" + +python do_display_banner() { + bb.plain("***********************************************"); + bb.plain("* *"); + bb.plain("* Example recipe created by bitbake-layers *"); + bb.plain("* *"); + bb.plain("***********************************************"); +} + +addtask display_banner before do_build diff --git a/recipes-kernel/linux/files/0001-arm64-Add-SomDevices-Smarc-C0P1-to-Makefile.patch b/recipes-kernel/linux/files/0001-arm64-Add-SomDevices-Smarc-C0P1-to-Makefile.patch new file mode 100644 index 0000000..f3de74f --- /dev/null +++ b/recipes-kernel/linux/files/0001-arm64-Add-SomDevices-Smarc-C0P1-to-Makefile.patch @@ -0,0 +1,24 @@ +From 17a4ba640e3dc5759559420b295db1e1edb6cef4 Mon Sep 17 00:00:00 2001 +From: OpenEmbedded +Date: Sun, 25 Jul 2021 21:27:32 +0000 +Subject: [PATCH] arm64: dts: Add SomDevices Smarc C0P1 to Makefile + +--- + arch/arm64/boot/dts/freescale/Makefile | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile +index 177d8c269134..239edfaeb895 100644 +--- a/arch/arm64/boot/dts/freescale/Makefile ++++ b/arch/arm64/boot/dts/freescale/Makefile +@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb + ++dtb-$(CONFIG_ARCH_MXC) += imx8mm-somdevices-c0p1.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \ + imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb imx8mm-evk-revb-qca-wifi.dtb \ +-- +2.25.1 + diff --git a/recipes-kernel/linux/files/0002-arm64-Add-sn65dsi83-4-support.patch b/recipes-kernel/linux/files/0002-arm64-Add-sn65dsi83-4-support.patch new file mode 100644 index 0000000..a53e7e5 --- /dev/null +++ b/recipes-kernel/linux/files/0002-arm64-Add-sn65dsi83-4-support.patch @@ -0,0 +1,1040 @@ +From 4054ba5246dee5b87fff9060e2b6ecdcda048f2c Mon Sep 17 00:00:00 2001 +From: OpenEmbedded +Date: Tue, 3 Aug 2021 18:39:30 +0000 +Subject: [PATCH] arm64: Add sn65dsi83-4 support + +--- + drivers/gpu/drm/bridge/Kconfig | 2 + + drivers/gpu/drm/bridge/Makefile | 1 + + drivers/gpu/drm/bridge/sn65dsi83/Kconfig | 6 + + drivers/gpu/drm/bridge/sn65dsi83/Makefile | 2 + + .../gpu/drm/bridge/sn65dsi83/sn65dsi83_brg.c | 422 +++++++++++++++++ + .../gpu/drm/bridge/sn65dsi83/sn65dsi83_brg.h | 63 +++ + .../gpu/drm/bridge/sn65dsi83/sn65dsi83_drv.c | 429 ++++++++++++++++++ + .../drm/bridge/sn65dsi83/sn65dsi83_timing.h | 38 ++ + 8 files changed, 963 insertions(+) + create mode 100644 drivers/gpu/drm/bridge/sn65dsi83/Kconfig + create mode 100644 drivers/gpu/drm/bridge/sn65dsi83/Makefile + create mode 100644 drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_brg.c + create mode 100644 drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_brg.h + create mode 100644 drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_drv.c + create mode 100644 drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_timing.h + +diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig +index 7e15d7c41eed..d71108c2a29b 100644 +--- a/drivers/gpu/drm/bridge/Kconfig ++++ b/drivers/gpu/drm/bridge/Kconfig +@@ -277,3 +277,5 @@ config DRM_ITE_IT6263 + ITE IT6263 bridge chip driver. + + endmenu ++ ++source "drivers/gpu/drm/bridge/sn65dsi83/Kconfig" +diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile +index 17d70fc62f89..795f34388f70 100644 +--- a/drivers/gpu/drm/bridge/Makefile ++++ b/drivers/gpu/drm/bridge/Makefile +@@ -31,3 +31,4 @@ obj-y += synopsys/ + obj-$(CONFIG_DRM_ITE_IT6263) += it6263.o + obj-$(CONFIG_DRM_SEC_MIPI_DSIM) += sec-dsim.o + obj-$(CONFIG_DRM_NXP_SEIKO_43WVFIG) += nxp-seiko-43wvfig.o ++obj-$(CONFIG_DRM_I2C_SN65DSI83) += sn65dsi83/ +diff --git a/drivers/gpu/drm/bridge/sn65dsi83/Kconfig b/drivers/gpu/drm/bridge/sn65dsi83/Kconfig +new file mode 100644 +index 000000000000..e1b8e802f61f +--- /dev/null ++++ b/drivers/gpu/drm/bridge/sn65dsi83/Kconfig +@@ -0,0 +1,6 @@ ++config DRM_I2C_SN65DSI83 ++ bool "TI SN65DSI83 MIPI DSI to LVDS bridge" ++ depends on OF ++ select DRM_MIPI_DSI ++ help ++ TI SN65DSI83 MIPI DSI to LVDS bridge driver +diff --git a/drivers/gpu/drm/bridge/sn65dsi83/Makefile b/drivers/gpu/drm/bridge/sn65dsi83/Makefile +new file mode 100644 +index 000000000000..dee7f493b323 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/sn65dsi83/Makefile +@@ -0,0 +1,2 @@ ++sn65dsi83-objs := sn65dsi83_drv.o sn65dsi83_brg.o ++obj-$(CONFIG_DRM_I2C_SN65DSI83) := sn65dsi83.o +diff --git a/drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_brg.c b/drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_brg.c +new file mode 100644 +index 000000000000..211c7fcb3e53 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_brg.c +@@ -0,0 +1,422 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018 CopuLab Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include