From 290687f13dfb7225f1a73082468b0e4c1044d4a4 Mon Sep 17 00:00:00 2001 From: Florin Chiculita Date: Tue, 6 Nov 2018 18:38:45 +0200 Subject: [PATCH] net/phy: Cortina CS4223 PHY support & bugfixes Cortina CS4223 PHY support based on software reference API. User configurable parameters for EDC mode and traceloss parameters. Defaults to optical settings. Fix for coarse tune VCO when refclk is not at 106MHz. Signed-off-by: Florin Chiculita Signed-off-by: Ioana Ciornei # rebased over v2021.04 --- drivers/net/phy/Makefile | 2 +- drivers/net/phy/cortina.c | 184 +- drivers/net/phy/cortina_api.c | 8078 +++++++++++++++++++++++++++++++++ include/cortina_api.h | 2822 ++++++++++++ 4 files changed, 11082 insertions(+), 4 deletions(-) create mode 100644 drivers/net/phy/cortina_api.c create mode 100644 include/cortina_api.h diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index e967f82201..b56a672b06 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_PHYLIB_10G) += generic_10g.o obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o obj-$(CONFIG_PHY_ATHEROS) += atheros.o obj-$(CONFIG_PHY_BROADCOM) += broadcom.o -obj-$(CONFIG_PHY_CORTINA) += cortina.o +obj-$(CONFIG_PHY_CORTINA) += cortina.o cortina_api.o obj-$(CONFIG_PHY_CORTINA_ACCESS) += ca_phy.o obj-$(CONFIG_PHY_DAVICOM) += davicom.o obj-$(CONFIG_PHY_ET1011C) += et1011c.o diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index b381a431fd..37a68bb9ac 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Cortina CS4315/CS4340 10G PHY drivers + * Cortina CS4223 40G PHY driver * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018, 2020 NXP + * Copyright 2018-2021 NXP * */ @@ -17,6 +18,7 @@ #include #include #include +#include #ifdef CONFIG_SYS_CORTINA_FW_IN_NAND #include #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) @@ -24,11 +26,16 @@ #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) #include #endif +#include #ifndef CONFIG_PHYLIB_10G #error The Cortina PHY needs 10G support #endif +/* Cortina CS4223 EQ & driver traceloss defaults */ +#define CS4223_LINE_DEFAULT_TRACELOSS CS_HSIO_TRACE_LOSS_4dB +#define CS4223_HOST_DEFAULT_TRACELOSS CS_HSIO_TRACE_LOSS_4dB + #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD struct cortina_reg_config cortina_reg_cfg[] = { /* CS4315_enable_sr_mode */ @@ -291,14 +298,185 @@ int cs4340_startup(struct phy_device *phydev) return 0; } +int cs4223_phy_setup(struct phy_device *phydev) +{ + int status = CS_OK; + struct cs4224_rules_t rules; + unsigned int slice = 0; + char *env_host_driver_ptr = env_get("cs4223_host_gain"); + char *env_host_eq_ptr = env_get("cs4223_host_eq"); + char *env_host_edc_ptr = env_get("cs4223_host_edc"); + char *env_line_driver_ptr = env_get("cs4223_line_gain"); + char *env_line_eq_ptr = env_get("cs4223_line_eq"); + char *env_line_edc_ptr = env_get("cs4223_line_edc"); + + char *env_autoconfig_ptr = env_get("cs4223_autoconfig"); + int autoconfig_success = 0; + int mseq_dyn_reconfig = CS_FALSE; + + int host_driver_settings = CS4223_HOST_DEFAULT_TRACELOSS; + int host_eq_settings = CS4223_HOST_DEFAULT_TRACELOSS; + int host_edc_mode = CS_HSIO_EDC_MODE_CX1; + + int line_driver_settings = CS4223_LINE_DEFAULT_TRACELOSS; + int line_eq_settings = CS4223_LINE_DEFAULT_TRACELOSS; + int line_edc_mode = CS_HSIO_EDC_MODE_SR; + + cs4223_glue_phydev_set(phydev); + + status |= cs4224_hard_reset(slice); + if (status != CS_OK) { + printf("error trying to reset the device\n"); + return status; + } + + if (env_autoconfig_ptr) { + if (!strncmp(env_autoconfig_ptr, "copper", 6)) { + line_edc_mode = CS_HSIO_EDC_MODE_CX1; + host_edc_mode = CS_HSIO_EDC_MODE_CX1; + host_driver_settings = CS_HSIO_TRACE_LOSS_4dB; + host_eq_settings = CS_HSIO_TRACE_LOSS_4dB; + line_driver_settings = CS_HSIO_TRACE_LOSS_6dB; + line_eq_settings = CS_HSIO_TRACE_LOSS_6dB; + mseq_dyn_reconfig = CS_TRUE; + autoconfig_success = 1; + } + + if (!strncmp(env_autoconfig_ptr, "optical", 7)) { + line_edc_mode = CS_HSIO_EDC_MODE_SR; + host_edc_mode = CS_HSIO_EDC_MODE_CX1; + host_driver_settings = CS_HSIO_TRACE_LOSS_4dB; + host_eq_settings = CS_HSIO_TRACE_LOSS_4dB; + line_driver_settings = CS_HSIO_TRACE_LOSS_4dB; + line_eq_settings = CS_HSIO_TRACE_LOSS_4dB; + mseq_dyn_reconfig = CS_FALSE; + autoconfig_success = 1; + } + } + + if (autoconfig_success) { + printf("CS4223: setting defaults for %s medium type...\n", + env_autoconfig_ptr); + goto skip_config; + } + + if (env_host_driver_ptr) { + host_driver_settings = + simple_strtoul(env_host_driver_ptr, NULL, 10); + + if ((host_driver_settings < CS_HSIO_TRACE_LOSS_0dB) || + (host_driver_settings > CS_HSIO_TRACE_LOSS_6dB)) { + printf("CS4223: host driver settings (%ddB) not ", + host_driver_settings); + printf("supported. Using defaults.\n"); + host_driver_settings = CS4223_HOST_DEFAULT_TRACELOSS; + } else { + host_eq_settings = host_driver_settings; + } + } + + if (env_line_driver_ptr) { + line_driver_settings = + simple_strtoul(env_line_driver_ptr, NULL, 10); + + if ((line_driver_settings < CS_HSIO_TRACE_LOSS_0dB) || + (line_driver_settings > CS_HSIO_TRACE_LOSS_6dB)) { + printf("CS4223: line driver settings (%ddB) not ", + line_driver_settings); + printf("supported. Using defaults.\n"); + line_driver_settings = CS4223_LINE_DEFAULT_TRACELOSS; + } else { + line_eq_settings = line_driver_settings; + } + } + + if (env_host_eq_ptr) { + host_eq_settings = simple_strtoul(env_host_eq_ptr, NULL, 10); + if ((host_eq_settings < CS_HSIO_TRACE_LOSS_0dB) || + (host_eq_settings > CS_HSIO_TRACE_LOSS_6dB)) { + printf("CS4223: host EQ traceloss (%ddB) not supported", + host_eq_settings); + printf(". Matching driver settings or defaults.\n"); + host_eq_settings = host_driver_settings; + } + } + + if (env_line_eq_ptr) { + line_eq_settings = simple_strtoul(env_line_eq_ptr, NULL, 10); + if ((line_eq_settings < CS_HSIO_TRACE_LOSS_0dB) || + (line_eq_settings > CS_HSIO_TRACE_LOSS_6dB)) { + printf("CS4223: line EQ traceloss (%ddB) not supported", + line_eq_settings); + printf(". Matching driver settings or defaults.\n"); + line_eq_settings = line_driver_settings; + } + } + + if (env_line_edc_ptr) { + if (!strncmp(env_line_edc_ptr, "cx", 2)) + line_edc_mode = CS_HSIO_EDC_MODE_CX1; + + if (!strncmp(env_line_edc_ptr, "sr", 2)) + line_edc_mode = CS_HSIO_EDC_MODE_SR; + } + + if (env_host_edc_ptr) { + if (!strncmp(env_host_edc_ptr, "cx", 2)) + host_edc_mode = CS_HSIO_EDC_MODE_CX1; + + if (!strncmp(env_host_edc_ptr, "sr", 2)) + host_edc_mode = CS_HSIO_EDC_MODE_SR; + } + +skip_config: + printf("CS4223: edc/gain/equalization settings: "); + printf("host: %s/%ddB/%ddB, line: %s/%ddB/%ddB\n", + host_edc_mode == CS_HSIO_EDC_MODE_CX1 ? "CX" : "SR", + host_driver_settings, + host_eq_settings, + line_edc_mode == CS_HSIO_EDC_MODE_CX1 ? "CX" : "SR", + line_driver_settings, + line_eq_settings); + + memset(&rules, 0, sizeof(struct cs4224_rules_t)); + status |= cs4224_rules_set_default(CS4224_TARGET_APPLICATION_10G, + &rules); + + if (host_edc_mode == CS_HSIO_EDC_MODE_CX1 && + line_edc_mode == CS_HSIO_EDC_MODE_CX1) + mseq_dyn_reconfig = CS_TRUE; + else + mseq_dyn_reconfig = CS_FALSE; + + rules.mseq_dyn_reconfig = mseq_dyn_reconfig; + rules.rx_if.dplx_line_edc_mode = line_edc_mode; + rules.rx_if.dplx_line_eq.traceloss = line_eq_settings; + rules.tx_if.dplx_line_driver.traceloss = line_driver_settings; + rules.rx_if.dplx_host_edc_mode = host_edc_mode; + rules.rx_if.dplx_host_eq.traceloss = host_eq_settings; + rules.tx_if.dplx_host_driver.traceloss = host_driver_settings; + + for (slice = 0; slice < CS4224_MAX_NUM_SLICES(0); slice++) + status |= cs4224_slice_enter_operational_state(slice, &rules); + + return status; +} + int cs4223_phy_init(struct phy_device *phydev) { int reg_value; + int status; reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) { - printf("%s CS4223 Firmware not present in EERPOM\n", __func__); - return -ENOSYS; + printf("\nCS4223: Using software initialization...\n"); + status = cs4223_phy_setup(phydev); + if (status != CS_OK) + printf("CS4223: Software initialization had issues!\n"); + + } else { + printf("\nCS4223: WARNING: Using EEPROM configuration...\n"); + printf("CS4223: WARNING: Change SW2[2] for software config\n"); } return 0; diff --git a/drivers/net/phy/cortina_api.c b/drivers/net/phy/cortina_api.c new file mode 100644 index 0000000000..6943f93d36 --- /dev/null +++ b/drivers/net/phy/cortina_api.c @@ -0,0 +1,8078 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Cortina PHY drivers framework + * + * Copyright 2018-2021 NXP + * Copyright (C) 2006-2017 Inphi Corporation, Inc. All rights reserved. + */ + +#include "cortina_api.h" + +static struct phy_device *cs4223_phydev; +static struct mii_dev *cs4223_bus; + +void cs4223_glue_phydev_set(struct phy_device *phydev) +{ + cs4223_phydev = phydev; + cs4223_bus = phydev->bus; +} + +int cs4224_reg_set(unsigned int slice, + unsigned int addr, + unsigned short data) +{ + cs4223_bus->write(cs4223_bus, 0, 0, addr, data); + return CS_OK; +} + +int cs4224_reg_get(unsigned int slice, + unsigned int addr, + unsigned short *data) +{ + *data = cs4223_bus->read(cs4223_bus, 0, 0, addr); + return CS_OK; +} + +unsigned char cs4224_diags_register_can_read(unsigned short addr) +{ + /* don't read from select register ranges */ + if ((addr >= CS4224_PP_LINE_SDS_DSP_MSEQ_IX && + addr <= CS4224_PP_LINE_SDS_DSP_MSEQ_BASE3_INST) || + (addr >= CS4224_PP_HOST_SDS_DSP_MSEQ_IX && + addr <= CS4224_PP_HOST_SDS_DSP_MSEQ_BASE3_INST)) { + return CS_FALSE; + } + return CS_TRUE; +} + +#if !defined(CS_SKIP_UCODE_DOWNLOAD) +/* The following array contains the microcode image to download + * to the device. It consists of a series of register writes + * in the format: + * address, data + */ +unsigned short cs4224_kr_ucode_image[] = { + 0x0011, 0x0001, 0x0017, 0x8080, 0x1091, 0x0001, 0x1007, 0x8004, 0x1225, + 0x0008, 0x1238, 0x0000, 0x0301, 0x9000, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x7c0d, 0x0302, 0x0084, 0x0303, 0x7c02, 0x0302, + 0x0088, 0x0303, 0x010d, 0x0302, 0x0060, 0x0303, 0x7c02, 0x0302, 0x0009, + 0x0303, 0x019f, 0x0302, 0x00e0, 0x0303, 0x7c02, 0x0302, 0x008d, 0x0303, + 0x0187, 0x0302, 0x00e0, 0x0303, 0x7c02, 0x0302, 0x00af, 0x0303, 0x01ea, + 0x0302, 0x0060, 0x0303, 0x7c02, 0x0302, 0x002e, 0x0303, 0x016d, 0x0302, + 0x0060, 0x0303, 0xc167, 0x0302, 0x0003, 0x0303, 0x0180, 0x0302, 0x0060, + 0x0303, 0x016d, 0x0302, 0x0060, 0x0303, 0xe805, 0x0302, 0x008d, 0x0303, + 0x4804, 0x0302, 0x008c, 0x0303, 0xc167, 0x0302, 0x0003, 0x0303, 0xc068, + 0x0302, 0x0083, 0x0303, 0x001b, 0x0302, 0x0000, 0x0303, 0xc067, 0x0302, + 0x0083, 0x0303, 0xc168, 0x0302, 0x0003, 0x0303, 0x6893, 0x0302, 0x0083, + 0x0303, 0x000b, 0x0302, 0x00ba, 0x0303, 0x9002, 0x0302, 0x008c, 0x0303, + 0x000f, 0x0302, 0x003a, 0x0303, 0x03f6, 0x0302, 0x0003, 0x0303, 0x9002, + 0x0302, 0x008a, 0x0303, 0x6793, 0x0302, 0x0083, 0x0303, 0x9006, 0x0302, + 0x0009, 0x0303, 0x0708, 0x0302, 0x003a, 0x0303, 0x03f5, 0x0302, 0x0003, + 0x0303, 0x050b, 0x0302, 0x00ba, 0x0303, 0x03f6, 0x0302, 0x0003, 0x0303, + 0x002d, 0x0302, 0x0000, 0x0303, 0x9003, 0x0302, 0x0028, 0x0303, 0xe2f5, + 0x0302, 0x0003, 0x0303, 0x002d, 0x0302, 0x0000, 0x0303, 0xc8f5, 0x0302, + 0x0083, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0xe605, 0x0302, 0x002f, + 0x0303, 0xe6f5, 0x0302, 0x0083, 0x0303, 0x0000, 0x0302, 0x0093, 0x0303, + 0xe643, 0x0302, 0x009f, 0x0303, 0x03f6, 0x0302, 0x0003, 0x0303, 0xe7f9, + 0x0302, 0x0003, 0x0303, 0x0000, 0x0302, 0x0093, 0x0303, 0x8503, 0x0302, + 0x0086, 0x0303, 0x035f, 0x0302, 0x0003, 0x0303, 0x037a, 0x0302, 0x009e, + 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, 0x003c, 0x0302, 0x0041, 0x0303, + 0x7a5f, 0x0302, 0x009e, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, 0x0045, + 0x0302, 0x0080, 0x0303, 0x7b75, 0x0302, 0x0097, 0x0303, 0x004e, 0x0302, + 0x0041, 0x0303, 0xf970, 0x0302, 0x001c, 0x0303, 0x03f9, 0x0302, 0x0003, + 0x0303, 0x757b, 0x0302, 0x009e, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, + 0x7b5f, 0x0302, 0x0099, 0x0303, 0x035f, 0x0302, 0x0003, 0x0303, 0x003c, + 0x0302, 0x0000, 0x0303, 0x7b75, 0x0302, 0x0097, 0x0303, 0x004e, 0x0302, + 0x0041, 0x0303, 0xf970, 0x0302, 0x009d, 0x0303, 0x03f9, 0x0302, 0x0003, + 0x0303, 0x757b, 0x0302, 0x009e, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, + 0x5f7b, 0x0302, 0x001e, 0x0303, 0x035f, 0x0302, 0x0003, 0x0303, 0x0045, + 0x0302, 0x0080, 0x0303, 0xcc60, 0x0302, 0x0003, 0x0303, 0xdb68, 0x0302, + 0x0083, 0x0303, 0x000b, 0x0302, 0x00ba, 0x0303, 0x03db, 0x0302, 0x0011, + 0x0303, 0x03db, 0x0302, 0x0003, 0x0303, 0x0000, 0x0302, 0x0093, 0x0303, + 0x000f, 0x0302, 0x005a, 0x0303, 0x0381, 0x0302, 0x0003, 0x0303, 0xc375, + 0x0302, 0x0083, 0x0303, 0x00f6, 0x0302, 0x0060, 0x0303, 0xf467, 0x0302, + 0x0003, 0x0303, 0x4df4, 0x0302, 0x0097, 0x0303, 0x0056, 0x0302, 0x0041, + 0x0303, 0x0017, 0x0302, 0x009a, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, + 0x00f6, 0x0302, 0x0060, 0x0303, 0xf40f, 0x0302, 0x001f, 0x0303, 0x2267, + 0x0302, 0x0002, 0x0303, 0x4df4, 0x0302, 0x0097, 0x0303, 0x005b, 0x0302, + 0x00c1, 0x0303, 0x002b, 0x0302, 0x009a, 0x0303, 0x0375, 0x0302, 0x0083, + 0x0303, 0x00f6, 0x0302, 0x0060, 0x0303, 0xf472, 0x0302, 0x0083, 0x0303, + 0x4df4, 0x0302, 0x0097, 0x0303, 0x0062, 0x0302, 0x00c1, 0x0303, 0x003f, + 0x0302, 0x009a, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, 0x00f6, 0x0302, + 0x0060, 0x0303, 0xf40f, 0x0302, 0x001f, 0x0303, 0x2272, 0x0302, 0x0082, + 0x0303, 0x4df4, 0x0302, 0x0097, 0x0303, 0x0068, 0x0302, 0x00c1, 0x0303, + 0x720f, 0x0302, 0x009f, 0x0303, 0x4f75, 0x0302, 0x0082, 0x0303, 0x7567, + 0x0302, 0x0011, 0x0303, 0x03ec, 0x0302, 0x0083, 0x0303, 0x68db, 0x0302, + 0x0083, 0x0303, 0xc081, 0x0302, 0x0003, 0x0303, 0x00e6, 0x0302, 0x00ba, + 0x0303, 0x03f4, 0x0302, 0x0083, 0x0303, 0x03b2, 0x0302, 0x0003, 0x0303, + 0xcffe, 0x0302, 0x0083, 0x0303, 0xc2fd, 0x0302, 0x0003, 0x0303, 0x9015, + 0x0302, 0x000b, 0x0303, 0x780f, 0x0302, 0x009f, 0x0303, 0x0106, 0x0302, + 0x00e0, 0x0303, 0x0083, 0x0302, 0x0080, 0x0303, 0xfd03, 0x0302, 0x0004, + 0x0303, 0xc0fd, 0x0302, 0x0083, 0x0303, 0x0083, 0x0302, 0x0080, 0x0303, + 0xfe70, 0x0302, 0x001d, 0x0303, 0x03fe, 0x0302, 0x0083, 0x0303, 0xc1ae, + 0x0302, 0x0003, 0x0303, 0xc2ae, 0x0302, 0x0003, 0x0303, 0x6f0f, 0x0302, + 0x009f, 0x0303, 0x0106, 0x0302, 0x00e0, 0x0303, 0xc0ae, 0x0302, 0x0083, + 0x0303, 0xb100, 0x0302, 0x00af, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x01f4, 0x0302, 0x003a, 0x0303, 0xb003, + 0x0302, 0x0097, 0x0303, 0xfe02, 0x0302, 0x0009, 0x0303, 0x007e, 0x0302, + 0x0041, 0x0303, 0x00c0, 0x0302, 0x003a, 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0x0004, 0x0001, 0x0005, 0x0001, 0x0006, 0x0001, 0x0007, 0x0001, + 0x0301, 0x0000, 0x1320, 0x0000, 0x1324, 0x0000, 0x1328, 0x0000, 0x0017, + 0x0040, 0x1238, 0x0003, 0x1a38, 0x0003, 0x1249, 0x0001, 0x1343, 0x0006, + 0x1262, 0x007f, 0x1263, 0x007f, 0x1264, 0x007f, 0x1248, 0x8100, 0x1247, + 0x8010, 0x1268, 0x0002, 0x1282, 0x0005, 0x1288, 0x3000, 0x124c, 0x8001, + 0x1298, 0x0003, 0x1245, 0x8c0f, 0x10aa, 0xff5d, 0x1265, 0x001e, 0x1027, + 0x00dd, 0x12b1, 0x0000, 0x1a98, 0x0003, 0x18ae, 0x0441, 0x18a1, 0x0004, + 0x18a7, 0xdfff, 0x18a6, 0x000d, 0x1a45, 0x8c0f, 0x18aa, 0xff5d, 0x1a34, + 0x0002, 0x1a5e, 0x0000, 0x1a5f, 0x0700, 0x1a49, 0x0001, 0x1b43, 0x0006, + 0x1a65, 0x001e, 0x1a62, 0x007f, 0x1a63, 0x007f, 0x1a64, 0x007f, 0x1a48, + 0x8100, 0x1a47, 0x8010, 0x1a68, 0x0002, 0x1a82, 0x0014, 0x1a4c, 0x8001, + 0x1827, 0x00dd, 0x1a35, 0x01f7, 0x1ab1, 0x0000, 0x0017, 0x0000, 0x000a, + 0x0946, 0x0009, 0x2016, 0x0008, 0x0314, 0x0005, 0x0003, 0x0007, 0x0000, + 0x0011, 0x0000, 0x0014, 0x12cd, 0x0017, 0x0000, +}; + +unsigned int cs4224_kr_ucode_image_length = sizeof(cs4224_kr_ucode_image) + / sizeof(cs4224_kr_ucode_image[0]); + +#endif /* !CS_SKIP_UCODE_DOWNLOAD */ + +/* extern unsigned short g_cs4224_simplex_valid_mate_slice[]; */ +/* unsigned char cs4224_diags_register_can_read(unsigned short addr); */ + +static enum e_cs4224_hardware_id cs4224_sku_hw_id = CS4224_HW_UNDEF; + +int g_cs4224_mseq_stall_delay_us = 100; + +void cs4224_reset_static_state_for_slice(unsigned int slice) +{ + CS_TRACE(("resetting slice %d\n", slice)); +} + +void cs4224_reset_static_state(void) +{ + cs4224_reset_die_static_state(0); +} + +void cs4224_reset_die_static_state(unsigned int die) +{ + unsigned int upper_bits = die & 0xFFFFFF00; + unsigned int slice; + + for (slice = upper_bits; (slice & 0xFF) < CS4224_MAX_NUM_SLICES(die); + slice++) { + cs4224_reset_static_state_for_slice(slice); + } + + /* this forces the cached hw_id to be re-initialized */ + cs4224_sku_hw_id = CS4224_HW_UNDEF; +} + +int cs4224_init_api_version(unsigned int slice) +{ + int status = CS_OK; + unsigned short api_version; + + /* Program the API version number */ + api_version = (CS_API_VERSION_MAJOR & 0xF); + api_version <<= 4; + api_version |= (CS_API_VERSION_MINOR & 0xF); + api_version <<= 8; + api_version |= CS_API_VERSION_UPDATE; + status |= cs4224_reg_set_channel(slice, CS4224_GLOBAL_SCRATCH7, + api_version); + + return status; +} + +unsigned int cs4224_max_num_ports; +unsigned int cs4224_max_num_dies; + +unsigned int CS4224_MAX_NUM_PORTS(void) +{ + return CS4224_MAX_NUM_SLICES(0); +} + +unsigned int CS4224_MAX_NUM_SLICES(unsigned int slice) +{ + /* Determine the h/w ID in order to + * initialize the number of ports + */ + cs4224_hw_id(slice); + + /* Now that the number of ports has been identified + * just return the initialized value + */ + return cs4224_max_num_ports; +} + +unsigned int CS4224_MAX_NUM_DIES(unsigned int slice) +{ + cs4224_hw_id(slice); + return cs4224_max_num_dies; +} + +cs4224_callback_lock g_cs4224_callback_lock = NULL; +cs4224_callback_unlock g_cs4224_callback_unlock; + +void cs4224_set_callback_for_lock(cs4224_callback_lock callback) +{ + g_cs4224_callback_lock = callback; +} + +void cs4224_set_callback_for_unlock(cs4224_callback_unlock callback) +{ + g_cs4224_callback_unlock = callback; +} + +int cs4224_lock(unsigned int slice) +{ + if (!g_cs4224_callback_lock) + return CS_OK; + + return g_cs4224_callback_lock(slice); +} + +int cs4224_unlock(unsigned int slice) +{ + if (!g_cs4224_callback_unlock) + return CS_OK; + + return g_cs4224_callback_unlock(slice); +} + +enum e_cs4224_hardware_id cs4224_hw_id(unsigned int slice) +{ + if (cs4224_sku_hw_id == CS4224_HW_UNDEF) { + unsigned short sku; + int status = CS_OK; + + cs4224_lock(slice); + + status |= cs4224_reg_get(0 | (slice & 0xffffff00), + CS4224_EFUSE_PDF_SKU, &sku); + + cs4224_unlock(slice); + + if (status != CS_OK) { + CS_TRACE(("WARNING: Could not read SKU\n")); + sku = 0x0000; + } + + /* clear SKU bits [15:5] and [3] */ + sku &= 0x0017; + + /* If the EFUSE is not programmed then default to CS4343. + * Bit 5 will be set to 1 if the EFUSE is programmed. If it + * is not programmed it will 0. + */ + if ((sku & 0x10) != 0x10) { + unsigned short chip_id; + + /* Try reading the ASIC ID from the second die. If it + * returns a non valid value then assume this is a 4D + * part. If it is a 4D part then the ASIC ID should + * return 0xffff. A value of 0 probably means that we're + * running CS Explorer in offline mode. + */ + status |= cs4224_reg_get( + 1 | (slice & 0xffffff00), + CS4224_GLOBAL_CHIP_ID_MSB, &chip_id); + + if (chip_id == 0 || chip_id == 0x3e5) { + CS_TRACE(("WARNING: EFUSE not programmed\n")); + CS_TRACE(("WARNING: Defaulting to CS4243\n")); + + cs4224_sku_hw_id = CS4224_HW_CS4343; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4343_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4343_DIES; + } else { + CS_TRACE(("WARNING: EFUSE not programmed\n")); + CS_TRACE(("WARNING: Defaulting to CS4223\n")); + + cs4224_sku_hw_id = CS4224_HW_CS4223; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4223_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4223_DIES; + } + } + /* Otherwise check what SKU is programmed */ + else { + switch (sku) { + case CS4224_HW_CS4223: + /* 4 port duplex */ + cs4224_sku_hw_id = CS4224_HW_CS4223; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4223_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4223_DIES; + break; + case CS4224_HW_CS4224: + /* 16 port simplex */ + cs4224_sku_hw_id = CS4224_HW_CS4224; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4224_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4224_DIES; + break; + case CS4224_HW_CS4221: + /* 10 port simplex */ + cs4224_sku_hw_id = CS4224_HW_CS4221; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4221_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4221_DIES; + break; + case CS4224_HW_CS4227: + /* 2 port duplex */ + cs4224_sku_hw_id = CS4224_HW_CS4227; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4227_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4227_DIES; + break; + case CS4224_HW_CS4210: + /* 16 port simplex */ + cs4224_sku_hw_id = CS4224_HW_CS4210; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4210_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4210_DIES; + break; + case CS4224_HW_CS4341: + /* 8 port duplex */ + cs4224_sku_hw_id = CS4224_HW_CS4341; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4341_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4341_DIES; + break; + default: + /* SKU must be cs4343 or if undefined + * we default to 8 port duplex + */ + cs4224_sku_hw_id = CS4224_HW_CS4343; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4343_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4343_DIES; + break; + } + } + } + + return cs4224_sku_hw_id; +} + +unsigned char cs4224_is_hw_simplex(unsigned int slice) +{ + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + if ((hw_id == CS4224_HW_CS4224) || + (hw_id == CS4224_HW_CS4221) || + (hw_id == CS4224_HW_CS4210)) { + return CS_TRUE; + } + return CS_FALSE; +} + +unsigned char cs4224_is_hw_duplex(unsigned int slice) +{ + /* only keep the 'list' of simplex/duplex slices in one place */ + if (cs4224_is_hw_simplex(slice)) + return CS_FALSE; + + return CS_TRUE; +} + +unsigned short cs4224_pp_sku_cs4343_offset[8] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x1000, 0x2000, 0x3000, 0x3000, 0x2000, 0x1000, 0x0000 +}; + +unsigned short cs4224_mseq_sku_cs4343_offset[8] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x0000, 0x100, 0x100, 0x0100, 0x0100, 0x0000, 0x0000 +}; + +/* CS4224_HW_CS4224 16 port simplex + * CS4224_HW_CS4210 16 port simplex, 15G only + */ +unsigned short cs4224_pp_sku_cs4224_offset[16] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x1000, 0x3000, 0x1000, 0x2000, 0x0000, 0x3000, 0x2000, + /* slice 8, 9, 10, 11, 12, 13, 14, 15 */ + 0x0000, 0x2000, 0x1000, 0x3000, 0x2000, 0x0000, 0x1000, 0x3000 +}; + +unsigned short cs4224_mseq_sku_cs4224_offset[16] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x0000, 0x0100, 0x0000, 0x0100, 0x0000, 0x0100, 0x0100, + /* slice 8, 9, 10, 11, 12, 13, 14, 15 */ + 0x0000, 0x0100, 0x0000, 0x0100, 0x0100, 0x0000, 0x0000, 0x0100 +}; + +/* CS4224_HW_CS4221 10 port simplex + * Relative to CS4224, CS4221 is mapped: + * CS4221 CS4224 + * Port Port + * 0 1 + * 1 0 + * 2 3 + * 3 5 + * 4 6 + * 5 10 + * 6 9 + * 7 11 + * 8 13 + * 9 14 + */ +unsigned short cs4224_pp_sku_cs4221_offset[10] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x1000, 0x0000, 0x1000, 0x0000, 0x3000, 0x1000, 0x2000, 0x3000, + /* slice 8, 9, */ + 0x0000, 0x1000 +}; + +unsigned short cs4224_mseq_sku_cs4221_offset[10] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0000, 0x0100, 0x0100, + /* slice 8, 9, */ + 0x0000, 0x0000 +}; + +unsigned int cs4224_adj_pp(unsigned int slice, unsigned short addr) +{ + unsigned short adj_addr = addr; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + switch (hw_id) { + case CS4224_HW_CS4223: /* 4 port duplex */ + + if ((slice & 0xFF) > 3) { + CS_TRACE(("ERROR: Duplex slice arg > 3, slice=0x%x\n", + slice)); + } + /* same mapping as cs4343 */ + adj_addr = (addr + cs4224_pp_sku_cs4343_offset[slice & 0x7]); + break; + + case CS4224_HW_CS4224: /* 16 port simplex */ + + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: Simplex slice arg > 15, slice=0x%x\n", + slice)); + } + adj_addr = (addr + cs4224_pp_sku_cs4224_offset[slice & 0xF]); + + break; + + case CS4224_HW_CS4343: /* 8 port duplex */ + + if ((slice & 0xFF) > 7) { + CS_TRACE(("ERROR: Duplex slice arg > 7, slice=0x%x\n", + slice)); + } + adj_addr = (addr + cs4224_pp_sku_cs4343_offset[slice & 0x7]); + + break; + + case CS4224_HW_CS4221: /* 10 port simplex */ + + if ((slice & 0xFF) > 9) { + CS_TRACE(("ERROR: Simplex slice arg > 9, slice=0x%x\n", + slice)); + adj_addr = (addr + cs4224_pp_sku_cs4221_offset[0]); + } else { + adj_addr = (addr + + cs4224_pp_sku_cs4221_offset[slice & 0xF]); + } + + break; + + case CS4224_HW_CS4227: /* 2 port duplex */ + + if ((slice & 0xFF) > 1) { + CS_TRACE(("ERROR: Duplex slice arg > 1, slice=0x%x\n", + slice)); + } + /* same mapping as cs4343 */ + adj_addr = (addr + cs4224_pp_sku_cs4343_offset[slice & 0x7]); + break; + + case CS4224_HW_CS4210: /* 16 port simplex */ + + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: Simplex slice arg > 15, slice=0x%x\n", + slice)); + } + adj_addr = (addr + cs4224_pp_sku_cs4224_offset[slice & 0xF]); + + break; + + case CS4224_HW_CS4341: /* 8 port duplex */ + if ((slice & 0xFF) > 7) { + CS_TRACE(("ERROR: Duplex slice arg > 7, slice=0x%x\n", + slice)); + } + adj_addr = (addr + cs4224_pp_sku_cs4343_offset[slice & 0x7]); + + break; + + default: + CS_TRACE(("ERROR: invalid hw_id: %x\n", hw_id)); + break; + } + + return adj_addr; +} + +unsigned int cs4224_adj_mseq(unsigned int slice, unsigned short addr) +{ + unsigned short adj_addr = addr; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + switch (hw_id) { + case CS4224_HW_CS4223: /* 4 port duplex */ + if ((slice & 0xFF) > 3) { + CS_TRACE(("ERROR: Duplex slice arg > 3, slice=%d\n", + slice)); + } + /* same mapping as cs4343 */ + adj_addr = (addr + cs4224_mseq_sku_cs4343_offset[slice & 0x7]); + break; + + case CS4224_HW_CS4224: /* 16 port simplex */ + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: Simplex slice arg > 15, slice=%d\n", + slice)); + } + adj_addr = (addr + cs4224_mseq_sku_cs4224_offset[slice & 0xF]); + + break; + + case CS4224_HW_CS4343: /* 8 port duplex */ + if ((slice & 0xFF) > 7) { + CS_TRACE(("ERROR: Duplex slice arg > 7, slice=%d\n", + slice)); + } + adj_addr = (addr + cs4224_mseq_sku_cs4343_offset[slice & 0x7]); + + break; + + case CS4224_HW_CS4221: /* 10 port simplex */ + if ((slice & 0xFF) > 9) { + CS_TRACE(("ERROR: Simplex slice arg > 9, slice=%d\n", + slice)); + adj_addr = (addr + cs4224_mseq_sku_cs4221_offset[0]); + } else { + adj_addr = (addr + + cs4224_mseq_sku_cs4221_offset[slice & 0xF]); + } + + break; + + case CS4224_HW_CS4227: /* 2 port duplex */ + if ((slice & 0xFF) > 1) { + CS_TRACE(("ERROR: Duplex slice arg > 1, slice=%d\n", + slice)); + } + /* same mapping as cs4343 */ + adj_addr = (addr + cs4224_mseq_sku_cs4343_offset[slice & 0x7]); + break; + + case CS4224_HW_CS4210: /* 16 port simplex */ + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: Simplex slice arg > 15, slice=%d\n", + slice)); + } + adj_addr = (addr + cs4224_mseq_sku_cs4224_offset[slice & 0xF]); + + break; + + case CS4224_HW_CS4341: /* 8 port duplex */ + if ((slice & 0xFF) > 7) { + CS_TRACE(("ERROR: Duplex slice arg > 7, slice=%d\n", + slice)); + } + adj_addr = (addr + cs4224_mseq_sku_cs4343_offset[slice & 0x7]); + + break; + + default: + CS_TRACE(("ERROR: invalid hw_id: %x\n", hw_id)); + break; + } + + return adj_addr; +} + +/* simplex mate slices (slices with the same PP number on the die) */ +unsigned short cs4224_mate_slice_sku_cs4224[16] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 5, 3, 6, 1, 7, 0, 2, 4, + /* slice 8, 9, 10, 11, 12, 13, 14, 15 */ + 13, 12, 14, 15, 9, 8, 10, 11 }; + +/* CS4221 has some 'empty' slices that don't have a mate slice, those must be + * handled manually, as there is no way to address them with reg_Xet_channel + */ +unsigned short cs4224_mate_slice_sku_cs4221[10] = { + /* slice 0, 1, 2, 3, 4 */ + 2, 3, 0, 1, 0xff, + /* slice 5, 6, 7, 8, 9 */ + 9, 0xff, 0xff, 0xff, 5 +}; + +int cs4224_simplex_mate_slice(unsigned int slice, unsigned int *mate) +{ + int status = CS_OK; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + unsigned char base_slice = (slice & 0xFF); + unsigned int upper_bits = (slice & 0xFFFFFF00); + + *mate = 0xFF; + + switch (hw_id) { + case CS4224_HW_CS4224: + case CS4224_HW_CS4210: /*16 port simplex*/ + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: slice parameter > 15\n")); + return CS_ERROR; + } + *mate = cs4224_mate_slice_sku_cs4224[base_slice]; + + break; + case CS4224_HW_CS4221: /*10 port simplex*/ + if ((slice & 0xFF) > 10) { + CS_TRACE(("ERROR: slice parameter > 10\n")); + return CS_ERROR; + } + *mate = cs4224_mate_slice_sku_cs4221[base_slice]; + + break; + default: + /* if duplex then just return the same slice, + * since that's technically correct + */ + *mate = base_slice; + + break; + } + + if (*mate == 0xFF) { + CS_TRACE(("ERROR: base_slice %d simplex mate missing\n", + base_slice)); + status |= CS_ERROR; + } + + *mate |= upper_bits; + + return status; +} + +unsigned char cs4224_line_rx_to_host_tx_dir(unsigned int slice) +{ + unsigned char lrx_to_htx = CS_TRUE; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + /* Mask off the upper bits in case they are set + * by the user. Otherwise the switch statement + * below won't work properly. + */ + slice = slice & 0xFF; + + if ((hw_id == CS4224_HW_CS4224) || (hw_id == CS4224_HW_CS4210)) { + /* 16 port simplex */ + switch (slice) { + case 0: + case 1: + case 2: + lrx_to_htx = CS_TRUE; + break; + + case 3: + lrx_to_htx = CS_FALSE; + break; + + case 4: + lrx_to_htx = CS_TRUE; + break; + + case 5: + case 6: + case 7: + lrx_to_htx = CS_FALSE; + break; + + case 8: + case 9: + case 10: + case 11: + lrx_to_htx = CS_TRUE; + break; + + case 12: + case 13: + case 14: + case 15: + lrx_to_htx = CS_FALSE; + break; + + default: + lrx_to_htx = CS_TRUE; + break; + } + } else if (hw_id == CS4224_HW_CS4221) { + /* 10 port simplex */ + switch (slice) { + case 0: + case 1: + lrx_to_htx = CS_TRUE; + break; + + case 2: + case 3: + case 4: + lrx_to_htx = CS_FALSE; + break; + + case 5: + case 6: + case 7: + lrx_to_htx = CS_TRUE; + break; + + case 8: + case 9: + lrx_to_htx = CS_FALSE; + break; + + default: + lrx_to_htx = CS_TRUE; + break; + } + } + + return lrx_to_htx; +} + +int cs4224_get_mseq_id(unsigned int slice, enum e_cs4224_mseq_id *mseq_id) +{ + int status = CS_OK; + + /* if mseq_id isn't simplex then just assume the user + * knows what they are doing + */ + if (cs4224_is_hw_simplex(slice) && *mseq_id == CS4224_SPLX_MSEQ) { + if (cs4224_line_rx_to_host_tx_dir(slice)) + *mseq_id = CS4224_DPLX_LINE_MSEQ; + else + *mseq_id = CS4224_DPLX_HOST_MSEQ; + } else { + if (*mseq_id == CS4224_SPLX_MSEQ) { + CS_TRACE(("ERROR: Duplex slice, invalid mseq_id\n")); + status |= CS_ERROR; + } + } + + return status; +} + +unsigned int cs4224_mseq_get_addr_offset(unsigned int slice, + enum e_cs4224_mseq_id mseq) +{ + unsigned int offset = 0; /* 0 is line side, 0x800 is host side */ + + if (cs4224_is_hw_simplex(slice) && mseq == CS4224_SPLX_MSEQ) { + if (!cs4224_line_rx_to_host_tx_dir(slice)) + offset = 0x800; + } else if (mseq == CS4224_DPLX_HOST_MSEQ) { + offset = 0x800; + } + + return offset; +} + +int cs4224_get_cfg_side(unsigned int slice, enum e_cs4224_cfg_sides_t *side) +{ + int status = CS_OK; + + /* a bit different than get_mseq_id, if you specify a non-simplex side + * then default to using that, otherwise use the Rx side of the simplex + * slice + */ + if (cs4224_is_hw_simplex(slice) && (*side == CS4224_CFG_SIMPLEX)) { + if (cs4224_line_rx_to_host_tx_dir(slice)) + *side = CS4224_CFG_LINE_SIDE; + else + *side = CS4224_CFG_HOST_SIDE; + } else { + if (*side == CS4224_CFG_SIMPLEX) { + CS_TRACE(("ERROR: Duplex slice, not simplex\n")); + status |= CS_ERROR; + } + } + + return status; +} + +int cs4224_mux_enable(unsigned int slice, + enum e_cs4224_cfg_sides_t side, + unsigned char enable) +{ + int status = CS_OK; + unsigned short stx0_misc_addr; + unsigned short data; + + if (side == CS4224_CFG_SIMPLEX) { + CS_TRACE(("ERROR: CS4224_CFG_SIMPLEX arg not supported\n")); + return CS_ERROR; + } + + if (side == CS4224_CFG_LINE_SIDE) + stx0_misc_addr = CS4224_PP_LINE_SDS_COMMON_STX0_MISC; + else + stx0_misc_addr = CS4224_PP_HOST_SDS_COMMON_STX0_MISC; + + cs4224_lock(slice); + + status |= cs4224_reg_get_channel(slice, stx0_misc_addr, &data); + if (enable) + data &= ~0x11; /* power-up mux, STX_EYEMODE_EN=0 */ + else + data |= 0x11; /* power-down mux, STX_EYEMODE_EN=1 */ + + status |= cs4224_reg_set_channel(slice, stx0_misc_addr, data); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_demux_enable(unsigned int slice, enum e_cs4224_cfg_sides_t side, + unsigned char enable) +{ + int status = CS_OK; + unsigned short mseq_power_down_addr; + unsigned short agc_config1_addr; + unsigned short data; + + if (side == CS4224_CFG_SIMPLEX) { + CS_TRACE(("ERROR: CS4224_CFG_SIMPLEX arg not supported\n")); + return CS_ERROR; + } + + if (side == CS4224_CFG_LINE_SIDE) { + mseq_power_down_addr = + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB; + agc_config1_addr = CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1; + } else { + mseq_power_down_addr = + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB; + agc_config1_addr = CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1; + } + + cs4224_lock(slice); + + cs4224_reg_get_channel(slice, agc_config1_addr, &data); + + /* Don't touch the power down registers if we're in CX1 mode */ + if (data != 0x5) { + if (enable) { + status |= cs4224_reg_get_channel( + slice, mseq_power_down_addr, &data); + data |= 0x001f; /* partial power-up */ + status |= cs4224_reg_set_channel( + slice, mseq_power_down_addr, data); + data &= ~0x001f; /* clear the partial power-up */ + data &= ~0x01c0; /* full power-up demux */ + status |= cs4224_reg_set_channel( + slice, mseq_power_down_addr, data); + } else { + status |= cs4224_reg_get_channel( + slice, mseq_power_down_addr, &data); + data |= 0x01c0; /* power-down demux */ + status |= cs4224_reg_set_channel( + slice, mseq_power_down_addr, data); + } + } + + cs4224_unlock(slice); + + return status; +} + +#define CS4224_SENSE_POINT_LOCAL_TEMPERATURE 1 << 0 +#define CS4224_SENSE_POINT_REMOTE_TEMPERATURE 1 << 1 +#define CS4224_SENSE_POINT_0p9_RX_VOLTAGE 1 << 2 +#define CS4224_SENSE_POINT_0p9_TX_VOLTAGE 1 << 3 +#define CS4224_SENSE_POINT_0p9_DIG_RX_VOLTAGE 1 << 4 +#define CS4224_SENSE_POINT_0p9_DIG_TX_VOLTAGE 1 << 5 +#define CS4224_SENSE_POINT_1p8_RX_VOLTAGE 1 << 6 +#define CS4224_SENSE_POINT_1p8_TX_VOLTAGE 1 << 7 +#define CS4224_SENSE_POINT_1p5_RX_VOLTAGE 1 << 8 +#define CS4224_SENSE_POINT_1p5_TX_VOLTAGE 1 << 9 + +int cs4224_enable_monitor_sense_points(unsigned int die, + unsigned char wait_till_stabilized) +{ + unsigned short reg_data; + int status = CS_OK; + + status |= cs4224_reg_get(die, CS4224_MONITOR_CONTROL0, ®_data); + + if (reg_data != 0x630F) { + status |= cs4224_reg_set(die, CS4224_MONITOR_CONFIG_MASK, + CS4224_SENSE_POINT_LOCAL_TEMPERATURE | + CS4224_SENSE_POINT_0p9_RX_VOLTAGE | + CS4224_SENSE_POINT_1p8_RX_VOLTAGE); + + status |= cs4224_reg_set(die, CS4224_MONITOR_CONTROL0, 0x630F); + + if (wait_till_stabilized) { + unsigned short reg_data; + int last = 0; + int i; + + /* Waiting for the monitors to stabilize */ + cs4224_reg_get(die, CS4224_MONITOR_STATUS_FINAL6, + ®_data); + + for (i = 0; i < 100; i++) { + CS_MDELAY(10); + + if (last > (int)reg_data) + break; + + last = (int)reg_data; + cs4224_reg_get(die, + CS4224_MONITOR_STATUS_FINAL6, + ®_data); + } + } + } + + return status; +} + +int cs4224_version(char *buffer, unsigned int buffer_len) +{ + CS_STRNCPY(buffer, + "CS4224 API Version " CS_API_VERSION "\n" + "Built on " CS_API_BUILD_DATE "\n", + buffer_len); + + return CS_OK; +} + +int cs4224_init_vco(unsigned int slice, unsigned int addr) +{ + int status = CS_OK; + unsigned short offset = 0; + unsigned short data = 0; + unsigned short i = 0; + + if (addr & CS4224_LINE_TO_HOST_OFFSET) + offset = CS4224_LINE_TO_HOST_OFFSET; + else + offset = 0; + + cs4224_lock(slice); + + /* re-initialize the VCO ALT coarse tuning algorithm + * to start searching for the correct frequency + */ + status |= cs4224_reg_set_channel(slice, addr, 0x2001); + status |= cs4224_reg_set_channel(slice, addr, 0xa001); + status |= cs4224_reg_set_channel(slice, addr, 0x2001); + + /* the worst-case time out value is where F(ref_clk) > F(vco_clk) so a + * timeout of 3.3ms should suffice for the completion of coarse tuning. + */ + for (i = 1500; i > 0; i--) { + /* check for CTVALID */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_STATUS + offset, + &data); + if ((data & CS_BIT15) || (status != CS_OK)) { + /* tuning done or error, exit */ + break; + } + CS_UDELAY(10); + } + cs4224_unlock(slice); + + if (i == 0) { + if (offset == 0) + CS_TRACE(("ERROR: Timeout slice %d Line VCO\n", slice)); + else + CS_TRACE(("ERROR: Timeout slice %d Host VCO\n", slice)); + + CS_TRACE(("ERROR: check CS_UDELAY implementation\n")); + status |= CS_ERROR; + } + + return status; +} + +int cs4224_gbl_clock_monitor(unsigned int slice, + struct cs4224_gbl_clk_mon_cfg_t *clk_mon_cfg) +{ + int status = CS_OK; + unsigned short data; + + CS_PRINTF(("Configuring the GBL clkmon\n")); + + data = clk_mon_cfg->clksel_divider | clk_mon_cfg->clksel_src; + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_CLKSEL, data); + + data = 0; + if (clk_mon_cfg->go) + data = 0x0002; + + if (clk_mon_cfg->free_run) + data |= 0x0010; + + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_CTRL, data); + + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_DURATION, + clk_mon_cfg->duration); + + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_MINTHRESH0, + clk_mon_cfg->min_thresh_0); + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_MINTHRESH1, + clk_mon_cfg->min_thresh_1); + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_MAXTHRESH0, + clk_mon_cfg->max_thresh_0); + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_MAXTHRESH1, + clk_mon_cfg->max_thresh_1); + + return status; +} + +void cs4224_pp_clk_mon_cfg_init(struct cs4224_pp_clk_mon_cfg_t *clk_mon_cfg) +{ + clk_mon_cfg->clksel_divider = CS4224_CLK_MON_DIV1; + clk_mon_cfg->clksel_src = CS4224_CLK_MON_PP_SRX; + clk_mon_cfg->go = CS_TRUE; + clk_mon_cfg->free_run = CS_TRUE; + clk_mon_cfg->duration = 0x4000; + clk_mon_cfg->min_thresh = 0; + clk_mon_cfg->max_thresh = 0; +} + +int cs4224_pp_clock_monitor(unsigned int slice, + enum e_cs4224_cfg_sides_t side, + struct cs4224_pp_clk_mon_cfg_t *clk_mon_cfg) +{ + int status = CS_OK; + unsigned short clksel_addr; + unsigned short ctrl_addr; + unsigned short duration_addr; + unsigned short min_thresh0_addr; + unsigned short min_thresh1_addr; + unsigned short max_thresh0_addr; + unsigned short max_thresh1_addr; + unsigned short data; + + status |= cs4224_get_cfg_side(slice, &side); + + if (side == CS4224_CFG_HOST_SIDE) { + clksel_addr = CS4224_PP_CLKMON_EGR_CLKSEL; + ctrl_addr = CS4224_PP_CLKMON_EGR_CTRL; + duration_addr = CS4224_PP_CLKMON_EGR_DURATION; + min_thresh0_addr = CS4224_PP_CLKMON_EGR_MINTHRESH0; + min_thresh1_addr = CS4224_PP_CLKMON_EGR_MINTHRESH1; + max_thresh0_addr = CS4224_PP_CLKMON_EGR_MAXTHRESH0; + max_thresh1_addr = CS4224_PP_CLKMON_EGR_MAXTHRESH1; + } else { + clksel_addr = CS4224_PP_CLKMON_ING_CLKSEL; + ctrl_addr = CS4224_PP_CLKMON_ING_CTRL; + duration_addr = CS4224_PP_CLKMON_ING_DURATION; + min_thresh0_addr = CS4224_PP_CLKMON_ING_MINTHRESH0; + min_thresh1_addr = CS4224_PP_CLKMON_ING_MINTHRESH1; + max_thresh0_addr = CS4224_PP_CLKMON_ING_MAXTHRESH0; + max_thresh1_addr = CS4224_PP_CLKMON_ING_MAXTHRESH1; + } + + data = clk_mon_cfg->clksel_divider | clk_mon_cfg->clksel_src; + status |= cs4224_reg_set_channel(slice, clksel_addr, data); + + status |= cs4224_reg_set_channel( + slice, + duration_addr, + clk_mon_cfg->duration); + + status |= cs4224_reg_set_channel( + slice, + min_thresh0_addr, + (unsigned short)clk_mon_cfg->min_thresh); + + status |= cs4224_reg_set_channel( + slice, + min_thresh1_addr, + (clk_mon_cfg->min_thresh >> 16)); + + status |= cs4224_reg_set_channel( + slice, + max_thresh0_addr, + (unsigned short)clk_mon_cfg->max_thresh); + + status |= cs4224_reg_set_channel( + slice, + max_thresh1_addr, + (clk_mon_cfg->max_thresh >> 16)); + + data = 0x0100; /* config */ + if (clk_mon_cfg->go) + data |= CS_BIT1; /* go */ + + if (clk_mon_cfg->free_run) + data |= CS_BIT4; /* free-run */ + + status |= cs4224_reg_set_channel(slice, ctrl_addr, data); + data &= ~CS_BIT1; /* clear go */ + status |= cs4224_reg_set_channel(slice, ctrl_addr, data); + + return status; +} + +int cs4224_pp_clock_monitor_freq_fixp( + unsigned int slice, enum e_cs4224_cfg_sides_t side, + struct cs4224_pp_clk_mon_cfg_t *pp_clk_mon_cfg, + unsigned int ref_clk_rate, + unsigned short *freq) +{ + int status = CS_OK; + signed char i = 0; + unsigned short data = 0; + unsigned int count = 0; + unsigned int ticks_per_sec = 0; + unsigned short des_freq = *freq; + unsigned char stalled = CS_FALSE; + unsigned short power_down = 0; + + unsigned short status_addr; + unsigned short count0_addr; + unsigned short count1_addr; + unsigned short power_down_addr; + enum e_cs4224_mseq_id mseq_id; + + status |= cs4224_get_cfg_side(slice, &side); + + if (side == CS4224_CFG_HOST_SIDE) { + status_addr = CS4224_PP_CLKMON_EGR_STATUS; + count0_addr = CS4224_PP_CLKMON_EGR_COUNT0; + count1_addr = CS4224_PP_CLKMON_EGR_COUNT1; + power_down_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB; + mseq_id = CS4224_DPLX_HOST_MSEQ; + } else { + status_addr = CS4224_PP_CLKMON_ING_STATUS; + count0_addr = CS4224_PP_CLKMON_ING_COUNT0; + count1_addr = CS4224_PP_CLKMON_ING_COUNT1; + power_down_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB; + mseq_id = CS4224_DPLX_LINE_MSEQ; + } + + status |= cs4224_query_mseq_is_stalled(slice, mseq_id, &stalled); + if (!stalled) + cs4224_mseq_stall(slice, mseq_id, CS_TRUE); + + status |= cs4224_reg_get_channel(slice, power_down_addr, &power_down); + if (power_down != 0x0000) { + status |= cs4224_reg_set_channel(slice, power_down_addr, 0x1f); + status |= cs4224_reg_set_channel(slice, power_down_addr, 0x00); + } + + /* setup clock mon */ + pp_clk_mon_cfg->clksel_divider = CS4224_CLK_MON_DIV1; + pp_clk_mon_cfg->go = CS_TRUE; + pp_clk_mon_cfg->free_run = CS_TRUE; + pp_clk_mon_cfg->duration = 0x4000; + + status |= cs4224_pp_clock_monitor(slice, side, pp_clk_mon_cfg); + + for (i = 10; i > 0; i--) { + status |= cs4224_reg_get_channel(slice, status_addr, &data); + if (data & 0x1) + break; + CS_UDELAY(200); /* 1/156.25MHz * 0x4000 = 154us */ + } + if (i <= 0) { + CS_TRACE(("ERROR: clock monitor count never completed\n")); + status |= CS_ERROR; + return status; + } + + status |= cs4224_reg_get_channel(slice, count1_addr, &data); + count = (unsigned int)data << 16; + status |= cs4224_reg_get_channel(slice, count0_addr, &data); + count |= (unsigned int)data; + + /* freq = count * ref * div / duration */ + /* control the truncating; don't loose precision unintentionally */ + ticks_per_sec = ((long long int)count * ref_clk_rate) / 1000; + + *freq = (ticks_per_sec * 1) / 0x4000; + + if (des_freq != 0) { + unsigned short temp = des_freq * 9; + + if ((*freq * 10) < temp) + CS_TRACE(("WARNING: freq < des_freq -10%%: %u < %u\n", + *freq, temp / 9)); + temp = des_freq * 11; + if ((*freq * 10) > temp) + CS_TRACE(("WARNING: freq > des_freq +10%%: %u > %u\n", + *freq, temp / 11)); + } + + if (power_down != 0x0000) + status |= cs4224_reg_set_channel(slice, power_down_addr, + power_down); + + if (!stalled) + cs4224_mseq_stall(slice, mseq_id, CS_FALSE); + + return status; +} + +int cs4224_init_ac_decoupling_caps(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short reg_data; + + if ((cs4224_is_hw_simplex(slice) && + cs4224_line_rx_to_host_tx_dir(slice)) || + (cs4224_is_hw_duplex(slice))) { + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4, + ®_data); + + if (rules->enable_ac_decoupling_caps) + reg_data |= 0x0080; + else + reg_data &= ~0x0080; + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4, + reg_data); + } + if ((cs4224_is_hw_simplex(slice) && + !cs4224_line_rx_to_host_tx_dir(slice)) || + (cs4224_is_hw_duplex(slice))) { + status |= cs4224_reg_get_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG4, + ®_data); + + if (rules->enable_ac_decoupling_caps) + reg_data |= 0x0080; + else + reg_data &= ~0x0080; + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG4, + reg_data); + } + + return status; +} + +int cs4224_rules_set_default(enum e_cs4224_target_application application, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + rules->application = application; + + rules->rx_if.splx_eq.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->rx_if.splx_edc_mode = CS_HSIO_EDC_MODE_SR; + + rules->tx_if.splx_driver.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->tx_if.splx_disable = CS_FALSE; + + rules->rx_if.dplx_line_eq.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->rx_if.dplx_host_eq.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->rx_if.dplx_line_edc_mode = CS_HSIO_EDC_MODE_SR; + rules->rx_if.dplx_host_edc_mode = CS_HSIO_EDC_MODE_SR; + + rules->tx_if.dplx_line_driver.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->tx_if.dplx_host_driver.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->tx_if.dplx_line_disable = CS_FALSE; + rules->tx_if.dplx_host_disable = CS_FALSE; + + rules->unsquelch_driver = CS_TRUE; + rules->tx_auto_squelch = CS_FALSE; + rules->enable_ac_decoupling_caps = CS_TRUE; + rules->enable_power_savings = CS_TRUE; + rules->enable_die_broadcast = CS_TRUE; + + /* By default leave debugging info disabled. Customers + * can turn this on if desired. + */ + rules->show_debug_info = CS_TRUE; + + /* By default turn off the ability of the microsequencer to + * perform a dynamic reconfig + */ + rules->mseq_dyn_reconfig = CS_FALSE; + + switch (application) { + case CS4224_TARGET_APPLICATION_OC12: + case CS4224_TARGET_APPLICATION_1G: + case CS4224_TARGET_APPLICATION_5G: + case CS4224_TARGET_APPLICATION_7p5G: + case CS4224_TARGET_APPLICATION_8G: + case CS4224_TARGET_APPLICATION_8p5G: + case CS4224_TARGET_APPLICATION_15G: + case CS4224_TARGET_APPLICATION_16G_FC: + case CS4224_TARGET_APPLICATION_10G_FC: + case CS4224_TARGET_APPLICATION_8G_FC: + case CS4224_TARGET_APPLICATION_4G_FC: + case CS4224_TARGET_APPLICATION_2G_FC: + case CS4224_TARGET_APPLICATION_1G_FC: + case CS4224_TARGET_APPLICATION_10G_KR: + case CS4224_TARGET_APPLICATION_40G_KR: + case CS4224_TARGET_APPLICATION_KRAN: + case CS4224_TARGET_APPLICATION_FCAN: + status = CS_ERROR; + printf("Application not yet supported\n"); + break; + case CS4224_TARGET_APPLICATION_10G: + /* 156.25MHz ref clock, 10.3125GHz */ + rules->ref_clk_rate = CS4224_REF_CLK_156p25; + + rules->clkdiv.enable = CS_TRUE; + rules->clkdiv.fastdiv = 0x3; /* div by 40 (default) */ + rules->clkdiv.ddiv = CS4224_DDIV_DIV1; + rules->clkdiv.rdiv = CS4224_RDIV_DIV66; + + break; + + default: { + CS_TRACE(("ERROR: Invalid application=%d\n", application)); + status = CS_ERROR; + break; + } + } + + return status; +} + +int cs4224_mseq_squelch_ctrl(unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned char enable) +{ + int status = CS_OK; + unsigned short offset = 0x0; + unsigned short spare12; + enum e_cs4224_mseq_id mate_mseq; + unsigned char stalled = CS_FALSE; + unsigned short data; + + status |= cs4224_get_cfg_side(slice, (enum e_cs4224_cfg_sides_t *)&dir); + if (status != CS_OK) + return status; + + if (dir == CS4224_LINE_RX_TO_HOST_TX_DIR) { + offset = 0x0; + mate_mseq = CS4224_DPLX_HOST_MSEQ; + } else { + offset = CS4224_LINE_TO_HOST_OFFSET; + mate_mseq = CS4224_DPLX_LINE_MSEQ; + } + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + offset, + &spare12); + + if (enable) { + if (cs4224_is_hw_simplex(slice)) { + status |= cs4224_query_mseq_is_stalled(slice, mate_mseq, + &stalled); + if (stalled) + status |= cs4224_mseq_stall(slice, mate_mseq, + CS_FALSE); + } + if (CS_IF_CLR(spare12, CS_BIT2)) { + /* enable MSEQ control of squelch */ + spare12 = CS_SET(spare12, CS_BIT2); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + + offset, + spare12); + } + } else { + if (spare12 & CS_BIT2) { + /* disable MSEQ control of squelch */ + spare12 = CS_CLR(spare12, CS_BIT2); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + + offset, + spare12); + + /* delay for mseq to catch up */ + CS_UDELAY(30); + + /* disable this interfaces mail-out */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB + + offset, + 0); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_MSB + + offset, + 0); + /* disable the connected interface's mail in */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_MSB - + offset, + &data); + data = CS_CLR(data, CS_BIT15 | CS_BIT12); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_MSB - + offset, + data); + } + } + + return status; +} + +int cs4224_send_squelch_request(unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned char squelch) +{ + int status = CS_OK; + unsigned short offset = 0; + + status |= cs4224_get_cfg_side(slice, (enum e_cs4224_cfg_sides_t *)&dir); + if (status != CS_OK) + return status; + + if (dir == CS4224_LINE_RX_TO_HOST_TX_DIR) + offset = 0; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + if (squelch) + /* enable squelch */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB + offset, + 0x8000); + else + /* disable squelch */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB + offset, + 0x0000); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_MSB + offset, + 0x9000); + + return status; +} + +int cs4224_squelch_driver(unsigned int slice, enum e_cs4224_cfg_sides_t side, + unsigned char squelch) +{ + int status = CS_OK; + unsigned short squelch_addr; + unsigned short ctrla_addr; + unsigned short ctrla_storage_addr; + unsigned short spare12_addr; + unsigned short ctrla_storage_dft; + unsigned short ctrla; + unsigned short spare12; + + /* Cannot use cs4224_get_cfg_side, that is for the Rx side, not Tx */ + if (cs4224_is_hw_simplex(slice) && (side == CS4224_CFG_SIMPLEX)) { + if (cs4224_line_rx_to_host_tx_dir(slice)) + side = CS4224_CFG_HOST_SIDE; + else + side = CS4224_CFG_LINE_SIDE; + } else { + if (side == CS4224_CFG_SIMPLEX) { + CS_TRACE(("ERROR: Duplex slice, not simplex\n")); + status |= CS_ERROR; + } + } + + if (side == CS4224_CFG_LINE_SIDE) { + squelch_addr = CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH; + ctrla_addr = CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA; + ctrla_storage_addr = + CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0; + spare12_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_LSB; + } else { + squelch_addr = CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH; + ctrla_addr = CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA; + ctrla_storage_addr = + CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0; + spare12_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB; + } + ctrla_storage_dft = + CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0_dft; + + status |= cs4224_reg_get_channel(slice, spare12_addr, &spare12); + if (spare12 & 4) { + CS_TRACE(("ERROR: Squelching controlled by microsequencer,")); + CS_TRACE(("call cs4224_mseq_squelch_ctrl to disable auto")); + CS_TRACE((" Tx squelch control on slice, or use ")); + CS_TRACE(("cs4224_send_squelch_request instead.\n")); + return CS_ERROR; + } + + if (squelch) { + /* enable squelch */ + + status |= cs4224_reg_get_channel(slice, ctrla_addr, &ctrla); + if (ctrla != 0x0000) { + /* save then clear ctrla */ + status |= cs4224_reg_set_channel( + slice, ctrla_storage_addr, ctrla); + status |= cs4224_reg_set_channel(slice, ctrla_addr, + 0x0000); + } + status |= cs4224_reg_set_channel(slice, squelch_addr, 0x0001); + } else { + /* disable squelch */ + + status |= cs4224_reg_get_channel(slice, ctrla_storage_addr, + &ctrla); + if (ctrla != ctrla_storage_dft) { + /* restore cltra */ + status |= cs4224_reg_set_channel(slice, ctrla_addr, + ctrla); + /* set cltra storage back to 0xcccc (default) */ + status |= cs4224_reg_set_channel( + slice, ctrla_storage_addr, ctrla_storage_dft); + } + status |= cs4224_reg_set_channel(slice, squelch_addr, 0x0000); + } + + return status; +} + +/* This method performs a hard reset of a single die. See the + * header file for details + */ +int cs4224_hard_reset_die(unsigned int die) +{ + int status = CS_OK; + unsigned int stride = 0; + unsigned short data = 0x0; + + /* Wait for EEPROM download (which will be running after reset) */ + status |= cs4224_wait_for_eeprom_finished(die, 2500, 1); + + cs4224_lock(die); + + /* Fix the MDIO_CONFIG register so accesses to MSEQ registers + * don't time out (bug 35875) + */ + if (cs4224_reg_set(die, CS4224_GLOBAL_MDIO_CONFIG, + CS4224_GLOBAL_MDIO_CONFIG_pref) != CS_OK) { + /* If there is something wrong with the comms then quit */ + CS_TRACE(("ERROR: Something wrong with reg get/set methods\n")); + return CS_ERROR; + } + + /* Blindly stall all the mseqs */ + for (stride = 0; stride < 0x4000; stride += 0x1000) { + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + stride, + 0x8004); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + stride, + 0x0008); + status |= cs4224_reg_set( + die, CS4224_PP_HOST_HOSTMISC_MSEQCLKCTRL + stride, + 0x8004); + status |= cs4224_reg_set( + die, CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS + stride, + 0x0008); + } + + /* Use broadcast to write to all the ports at once, + * which can't be used to stall the mseqs + */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + { + /* Reset all port-pairs (PP) on the die */ + status |= cs4224_reg_set(die, CS4224_PP_LINE_LINEMISC_CLKEN, + 0xFFFF); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x0000); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_SOFT_RESET, 0x0001); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG, 0x0007); + /* Fix common_tx_sr default (ACJTAG) (bug 37448) */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_SOFT_RESET, 0x0000); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG, 0x0000); + status |= cs4224_reg_set(die, CS4224_PP_LINE_LINEMISC_CLKEN, + 0x0000); + } + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + +#ifndef CS_DONT_USE_MPIF_SOFT_RESET + /* Reset a die of the ASIC. This write is self clearing */ + cs4224_reg_set(die, CS4224_GLOBAL_MPIF_SOFT_RESET, 0xDEAD); +#endif + + /* Wait for the EEPROM to finish downloading the die */ + status |= cs4224_wait_for_eeprom_finished(die, 2500, 1); + + /* Squelch all transmitters out of reset */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH, 0x1); + + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + + if (status == CS_OK) { + /* if everything worked, then set the scratch to say this die + * was successfully reset + */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + status |= cs4224_reg_set(die, CS4224_GLOBAL_SCRATCH6, + CS_SET(data, CS_BIT1)); + } + + cs4224_unlock(die); + + /* reset the API static-state */ + cs4224_reset_die_static_state(die); + + return status; +} + +/* This method performs a hard reset on the K2 package. See + * the header file for details + */ +int cs4224_hard_reset(unsigned int slice) +{ + int status = CS_OK; + unsigned int die = slice & 0xFFFFFF00; + + /* reset die 0, which is always present */ + status |= cs4224_hard_reset_die(die); + + if (CS4224_MAX_NUM_DIES(die) > 1) { + /* reset die 1, which is chip-dependent */ + status |= cs4224_hard_reset_die(die | 0x1); + } + + return status; +} + +int cs4224_mseq_enable_power_savings(unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char enable) +{ + int status = CS_OK; + unsigned short reg_data = 0; + unsigned short spare12 = 0; + unsigned short clkdiv_ctrl = 0; + enum e_cs4224_edc_mode edc_mode = CS_HSIO_EDC_MODE_DISABLED; + unsigned char stalled; + unsigned short offset = 0; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + offset = 0; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + /* get the edc mode */ + status |= cs4224_query_edc_mode(slice, mseq_id, &edc_mode); + /* see if the mseq is stalled */ + status |= cs4224_query_mseq_is_stalled(slice, mseq_id, &stalled); + /* check the power-savings state */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + offset, + &spare12); + + if (enable) { + /* ring oscillator can't have power savings enabled; allow one + * to turn it off but not on + */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG + offset, + ®_data); + if (reg_data & CS_BIT7) + return status; + + /* clkdiv helps us figure out the config of this Rx intf */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL + offset, + &clkdiv_ctrl); + + /* if the mseq is stalled or in SR mode then you need to control + * power savings manually + */ + if (stalled || (edc_mode == CS_HSIO_EDC_MODE_SR)) { + /* if the fracn is needed we need to make sure we don't + * turn it off! + */ + if ((clkdiv_ctrl & 0x000F) == 0x0009) + /*fracn used*/ + reg_data = 0x1e7; + else + /*fracn not used*/ + reg_data = 0x1f7; + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + + offset, + reg_data); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB + + offset, + 0x0); + } + + /* power savings enable bit */ + spare12 |= CS_BIT1; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + offset, + spare12); + } else { /* disable */ + /* if the mseq is stalled or in SR mode then you need to control + * power savings manually + */ + if (stalled || (edc_mode == CS_HSIO_EDC_MODE_SR)) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + + offset, + 0x65); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB + + offset, + 0x0); + } + + /* power savings bit */ + spare12 = CS_CLR(spare12, CS_BIT1); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + offset, + spare12); + + /* Delay while the mseq changes the power down reg */ + CS_UDELAY(50); + } + + return status; +} + +int cs4224_query_mseq_power_savings(unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char *enabled) +{ + int status = CS_OK; + unsigned short reg_data = 0; + unsigned int spare12_addr; + + *enabled = CS_FALSE; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + spare12_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB; + else + spare12_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_LSB; + + status |= cs4224_reg_get_channel(slice, spare12_addr, ®_data); + + if ((reg_data & 0x2) == 0x2) + *enabled = CS_TRUE; + else + *enabled = CS_FALSE; + + return status; +} + +int cs4224_query_mseq_is_stalled(unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char *stalled) +{ + int status = CS_OK; + unsigned short options_shadow_addr; + unsigned short data; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + options_shadow_addr = + CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW; + else + options_shadow_addr = + CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_SHADOW; + + status |= cs4224_reg_get_channel(slice, options_shadow_addr, &data); + + if (data == 0xbada) { + /* some kind of read issue with power savings */ + CS_TRACE(("ERROR: SDS_DSP_MSEQ_OPTIONS_SHADOW == 0xbada\n")); + return CS_ERROR; + } + + if ((data & 0x8) == 0x8) + *stalled = CS_TRUE; + else + *stalled = CS_FALSE; + + return status; +} + +int cs4224_clear_mailbox(unsigned int slice, enum e_cs4224_mseq_id mseq_id) +{ + int status = CS_OK; + unsigned short mailbox_in_addr, mailbox_out_addr; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) { + mailbox_in_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_LSB; + mailbox_out_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB; + } else { + mailbox_in_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_LSB; + mailbox_out_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_LSB; + } + + cs4224_lock(slice); + + /* clear the out mail box queues in case they have a squelch/un-squelch + * request in them + */ + status |= cs4224_reg_set_channel(slice, mailbox_out_addr, 0); + status |= cs4224_reg_set_channel(slice, mailbox_out_addr + 1, 0); + /* clear the in mail box queue request */ + status |= cs4224_reg_set_channel(slice, mailbox_in_addr, 0); + status |= cs4224_reg_set_channel(slice, mailbox_in_addr + 1, 0); + + cs4224_unlock(slice); + + return status; +} + +void cs4224_mseq_stall_set_delay(int us) +{ + g_cs4224_mseq_stall_delay_us = us; +} + +int cs4224_mseq_stall_get_delay(void) +{ + return g_cs4224_mseq_stall_delay_us; +} + +int cs4224_mseq_stall(unsigned int slice, enum e_cs4224_mseq_id mseq_id, + unsigned char stall) +{ + int status = CS_OK; + unsigned short reg_offset = 0x0; + unsigned short reg_data = 0; + unsigned short bank, spare12 = 0; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + reg_offset = 0x0; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + reg_offset, + &spare12); + + if (stall) { + /* this enables the clocks even if the mseq is powered-down */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + reg_offset, + 0x8004); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + reg_offset, + 0x0008); + + /* Delay after stalling the microsequencer to ensure any timers + * have expired + */ + CS_UDELAY(cs4224_mseq_stall_get_delay()); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_ENABLE + reg_offset, + 0x0000); + + /* When stalling the microsequencer need to revert MSEQ_SERDES + * to it's default value or it may get set temporarily to 0x3b + * by the slicer calibration + */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + ®_data); + reg_data &= ~0xf; /* don't overwrite custom filtr */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + reg_data); + } else { /* un-stall */ + /* clear the SNR control reg, see youtrack cs-170 */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_CTRL + reg_offset, + 0x0000); + + /* save the current bank */ + cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + &bank); + + /* force a bank change to trigger the clearing of the + * micro-sequencer power-down timer. See MSEQBANKSWAP reg for + * details + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0007); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0000); + + /* if slice configured for FC-AN. Note that KR-AN does not use + * this stall/un-stall method + */ + if (spare12 & 0x0020) { + if (mseq_id == CS4224_DPLX_LINE_MSEQ) { + /* In FC-AN mode the the LINE side bank select + * is initialized to 4 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR, + 0x0004); + } else { + /* In FC-AN mode the the HOST side bank select + * is initialized to 7 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_BANK_SELECTOR, + 0x0007); + } + } else { /* not FC-AN */ + /* Revert the bank-select in DFE mode. This will not + * work for protocol modes like KR-AN and FC-AN. + */ + if (bank == 3) { + /* In SR mode the bank select is fixed at 3. */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0003); + } else { + /* DFE modes */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0000); + } + } + + /* if the microsequencer triggered dynamic reconfig is enabled, + * then force the bank to 7 + */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB + reg_offset, + ®_data); + if (reg_data & 0x8000) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0007); + } + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + reg_offset, + 0x0004); + + /* Restore the datastore registers before un-stalling */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + 1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + 2 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + reg_offset, + 0x803c); + + /* reset the program counter and unstall */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_PC + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + reg_offset, + 0x0007); + } + + cs4224_unlock(slice); + + return status; +} + +int cs4224_mseqs_stall(struct cs4224_interface_t interfaces[], + unsigned short length, + unsigned char stall) +{ + int status = CS_OK; + unsigned short reg_data = 0; + unsigned short bank, spare12_lsb = 0; + unsigned int i = 0; + + for (i = 0; i < length; i++) { + unsigned short reg_offset = 0x0; + unsigned int slice = interfaces[i].slice; + enum e_cs4224_mseq_id mseq_id; + + /* first convert mseq_id to be either line/host, so we don't + * have to have this check in the next loop + */ + status |= cs4224_get_mseq_id(interfaces[i].slice, + &interfaces[i].mseq_id); + if (status != CS_OK) { + CS_TRACE(("ERROR: Converting interfaces\n")); + return status; + } + mseq_id = interfaces[i].mseq_id; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + reg_offset = 0x0; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + if (stall) { + /* this enables the clocks even if the microsequencer is + * powered-down + */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + + reg_offset, + 0x8004); + + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + + reg_offset, + 0x0008); + + /* rest of stall code is after the loop */ + } else { /* un-stall */ + /* If the mseq is in control of squelch, set squelch + * right off the bat because the mseq starts off in a + * non EDC converged state. + */ + status |= + cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + + reg_offset, + &spare12_lsb); + if (spare12_lsb & CS_BIT2) { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH - + reg_offset, + 0x1); /* Tx side,inverse the mseq side*/ + } + + /* save the current bank */ + status |= + cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + &bank); + + /* force a bank change to trigger the clearing of the + * micro-sequencer power-down timer. See MSEQBANKSWAP + * reg for details + */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0007); + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0000); + + /* if slice configured for FC-AN. Note that KR-AN does + * not use this stall/un-stall method + */ + if (spare12_lsb & 0x0020) { + if (mseq_id == CS4224_DPLX_LINE_MSEQ) { + /* In FC-AN mode the the LINE side bank + * select is initialized to 4 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR, + 0x0004); + } else { + /* In FC-AN mode the the HOST side bank + * select is initialized to 7 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_BANK_SELECTOR, + 0x0007); + } + } else { + /* not FC-AN: Revert the bank-select in DFE + * mode. This will not work for protocol modes + * like KR-AN and FC-AN + */ + if (bank == 3) { + /* In SR mode the bank select is fixed + * at 3. + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0003); + } else { + /* DFE modes */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0000); + } + } + + /* if the microsequencer triggered dynamic reconfig is + * enabled, then force the bank to 7 + */ + status |= + cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB + + reg_offset, + ®_data); + if (reg_data & 0x8000) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0007); + } + /* rest of unstall code after the loop */ + } + cs4224_unlock(slice); + } + + if (stall) { + /* Delay after stalling the microsequencer to ensure any timers + * have expired + */ + CS_UDELAY(100); + } + + for (i = 0; i < length; i++) { + unsigned short reg_offset = 0x0; + unsigned int slice = interfaces[i].slice; + enum e_cs4224_mseq_id mseq_id = interfaces[i].mseq_id; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + reg_offset = 0x0; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + if (stall) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_ENABLE + reg_offset, + 0x0000); + + /* When stalling the microsequencer need to revert + * MSEQ_SERDES to it's default value or it may get set + * temporarily to 0x3b by the slicer calibration + */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + ®_data); + reg_data &= ~0xf; /* don't overwrite custom filtr */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + reg_data); + } else { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + + reg_offset, + 0x0004); + + /* Restore the datastore registers before un-stalling */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + 1 + + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + 2 + + reg_offset, + 0x0000); + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + + reg_offset, + 0x803c); + + /* reset the program counter and unstall */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_PC + reg_offset, + 0x0000); + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + + reg_offset, + 0x0007); + } + cs4224_unlock(slice); + } + + return status; +} + +int cs4224_init_global_timer_fixp(unsigned int slice, unsigned int ref_clk_freq) +{ + int status = CS_OK; + unsigned int ref_clk_per; + unsigned int num_clks; + + ref_clk_per = 1000000000L / ref_clk_freq; + num_clks = 100000000L / ref_clk_per; + + cs4224_lock(slice); + + status |= cs4224_reg_set_channel( + slice, CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT0, num_clks); + status |= cs4224_reg_set_channel( + slice, CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT1, num_clks >> 16); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_init_lc_vco_tmp_thresh(unsigned int slice, + enum e_cs4224_cfg_sides_t intf) +{ + int status = CS_OK; + unsigned short offset; + + if (intf == CS4224_CFG_LINE_SIDE) + offset = 0x0000; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + /* These thresholds valid for LC VCO only */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES00 + offset, + 0x13a); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES01 + offset, + 0x127); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES02 + offset, + 0x117); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES03 + offset, + 0x0); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES04 + offset, + 0x0); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES10 + offset, + 0x13f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES11 + offset, + 0x12f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES12 + offset, + 0x127); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES13 + offset, + 0x0); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES14 + offset, + 0x0); + + return status; +} + +int cs4224_init_ro_vco_tmp_thresh(unsigned int slice, + enum e_cs4224_cfg_sides_t intf) +{ + int status = CS_OK; + unsigned short offset; + + if (intf == CS4224_CFG_LINE_SIDE) + offset = 0x0000; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + /* These thresholds valid for Ring Oscillator VCO only */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES00 + offset, + 0x018f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES01 + offset, + 0x015f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES02 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES03 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES04 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES10 + offset, + 0x018f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES11 + offset, + 0x015f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES12 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES13 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES14 + offset, + 0x0000); + + return status; +} + +int cs4224_init_10g(unsigned int slice, enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short offset = 0; + + if (intf == CS4224_CFG_LINE_SIDE) + offset = 0x0000; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL2 + offset, + 0x1000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL1 + offset, + 0x0008); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_config_target_application_intf(unsigned int slice, + enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + status |= cs4224_get_cfg_side(slice, &intf); + if (status != CS_OK) + return status; + + switch (rules->application) { + case CS4224_TARGET_APPLICATION_5G: + case CS4224_TARGET_APPLICATION_7p5G: + case CS4224_TARGET_APPLICATION_8G: + case CS4224_TARGET_APPLICATION_8p5G: + case CS4224_TARGET_APPLICATION_10G_FC: + case CS4224_TARGET_APPLICATION_10G_KR: + case CS4224_TARGET_APPLICATION_40G_KR: + case CS4224_TARGET_APPLICATION_KRAN: + case CS4224_TARGET_APPLICATION_15G: + case CS4224_TARGET_APPLICATION_16G_FC: + case CS4224_TARGET_APPLICATION_8G_FC: + case CS4224_TARGET_APPLICATION_1G_FC: + case CS4224_TARGET_APPLICATION_2G_FC: + case CS4224_TARGET_APPLICATION_4G_FC: + case CS4224_TARGET_APPLICATION_FCAN: + case CS4224_TARGET_APPLICATION_OC12: + case CS4224_TARGET_APPLICATION_1G: + status = CS_ERROR; + break; + case CS4224_TARGET_APPLICATION_10G: + status |= cs4224_init_10g(slice, intf, rules); + break; + + default: + status = CS_ERROR; + break; + } + + return status; +} + +int cs4224_config_target_application(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) + status |= cs4224_config_target_application_intf( + slice, CS4224_CFG_LINE_SIDE, rules); + + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) + status |= cs4224_config_target_application_intf( + slice, CS4224_CFG_HOST_SIDE, rules); + + return status; +} + +int cs4224_pgm_reg_from_efuse(unsigned int slice, + enum e_cs4224_cfg_sides_t dir) +{ + int status = CS_OK; + unsigned short efuse_data0, efuse_data1, efuse_data2; + unsigned short cml_itune, cml_rtune; + unsigned short vco_itune; + unsigned short driver_rtune, driver_itune; + unsigned short agc_itune, agc_rtune; + unsigned short drivercml_rtune, drivercml_itune; + unsigned short reg_data, old_data; + unsigned int die = cs4224_get_die_from_slice(slice); + unsigned short reg_offset = 0x0000; + + cs4224_lock(slice); + + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_POLY_RES_CAL_DATA0, + &efuse_data0); + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_POLY_RES_CAL_DATA1, + &efuse_data1); + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_POLY_RES_CAL_DATA2, + &efuse_data2); + + if (dir == CS4224_CFG_LINE_SIDE) + reg_offset = 0; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + /* assign efuse cml_itune to + * PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE[2:0] + */ + cml_itune = efuse_data0 & 0x0070; + + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE + reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0007) | (cml_itune >> 4); + if (old_data != reg_data) { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE + + reg_offset, + reg_data); + } + + /* assign vco_itune to PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE[6:4] + * and cml_rtune to PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE[2:0] + */ + vco_itune = efuse_data0 & 0x7000; + cml_rtune = efuse_data1 & 0x7000; + + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE + reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0077) | (cml_rtune >> 12) | (vco_itune >> 8); + if (old_data != reg_data) { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE + + reg_offset, + reg_data); + } + + /* assign efuse agc_itune to + * CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2[6:4] + */ + agc_itune = efuse_data0 & 0x0007; + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2 + reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0xFF8F) | (agc_itune << 4); + if (old_data != reg_data) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2 + reg_offset, + reg_data); + } + + /* assign driver_rtune to + * CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_TUNE[10:8] and + * driver_itune to CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_TUNE[2:0] + */ + driver_rtune = efuse_data2 & 0x0070; + driver_itune = efuse_data1 & 0x0007; + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE - reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0707) | (driver_rtune << 4) + | (driver_itune >> 0); + if (old_data != reg_data) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE - reg_offset, + reg_data); + } + + /* assign drivercml_rtune to + * CS4224_PP_LINE_SDS_COMMON_STX0_DRIVERCML_TUNE[10:8] + * and drivercml_itune to + * CS4224_PP_LINE_SDS_COMMON_STX0_DRIVERCML_TUNE[2:0] + */ + drivercml_rtune = efuse_data2 & 0x0700; + drivercml_itune = efuse_data1 & 0x0070; + + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE - reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0707) | (drivercml_rtune << 0) + | (drivercml_itune >> 4); + if (old_data != reg_data) { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE - + reg_offset, + reg_data); + } + + /* assign efuse agc_itune to + * CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE[2:0] + */ + agc_rtune = efuse_data1 & 0x0700; + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE + reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0007) | (agc_rtune >> 8); + if (old_data != reg_data) + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE + reg_offset, + reg_data); + + /* the value for the dfe i/rtune should not be based on the + * E-Fuse setting + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG + reg_offset, + 0x1910); + + /* over-ride efuse data with registers */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_OVERRIDE_EN + reg_offset, + 0x0006); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_update_pre_equalizer(unsigned int slice, unsigned short reg_offset, + enum e_cs4224_trace_loss traceloss) +{ + int status = CS_OK; + unsigned short lim_eqadj; + unsigned short pass_eqadj1; + unsigned short pass_eqadj2; + + switch (traceloss) { + case CS_HSIO_TRACE_LOSS_0dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0001; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_1dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0000; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_2dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0001; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_3dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0004; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_4dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0005; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_5dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0006; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_6dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0007; + pass_eqadj2 = 0x070F; + break; + } + default: { + return CS_OK; + } + } + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_MISC + reg_offset, + lim_eqadj); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ1 + reg_offset, + pass_eqadj1); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ2 + reg_offset, + pass_eqadj2); + + return status; +} + +int cs4224_save_edc_mode(unsigned int slice, unsigned short reg_offset, + enum e_cs4224_edc_mode edc_mode) +{ + int status = CS_OK; + unsigned short saved_edc_mode; + + switch (edc_mode) { + case CS_HSIO_EDC_MODE_DISABLED: + saved_edc_mode = 0; + break; + case CS_HSIO_EDC_MODE_CX1: + saved_edc_mode = 1; + break; + case CS_HSIO_EDC_MODE_SR: + saved_edc_mode = 2; + break; + case CS_HSIO_EDC_MODE_ZR: + saved_edc_mode = 3; + break; + case CS_HSIO_EDC_MODE_DWDM: + saved_edc_mode = 4; + break; + case CS_HSIO_EDC_MODE_10G_BP: + saved_edc_mode = 5; + break; + case CS_HSIO_EDC_MODE_15G_BP: + saved_edc_mode = 6; + break; + case CS_HSIO_EDC_MODE_5G_BP: + saved_edc_mode = 7; + break; + case CS_HSIO_EDC_MODE_7p5G_BP: + saved_edc_mode = 8; + break; + case CS_HSIO_EDC_MODE_8p5G_BP: + saved_edc_mode = 9; + break; + case CS_HSIO_EDC_MODE_FCAN: + saved_edc_mode = 10; + break; + case CS_HSIO_EDC_MODE_15G_BP_27dB: + saved_edc_mode = 11; + break; + case CS_HSIO_EDC_MODE_SMLRM: + saved_edc_mode = 12; + break; + + default: + CS_TRACE(("ERROR: %s: slice = %d, ", __func__, slice)); + CS_TRACE(("unknown EDC mode = %d\n", edc_mode)); + status |= CS_ERROR; + saved_edc_mode = 1; + break; + } + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE2PRELOAD0 + reg_offset, + saved_edc_mode); + + return status; +} + +int cs4224_query_edc_mode(unsigned int slice, enum e_cs4224_mseq_id mseq_id, + enum e_cs4224_edc_mode *edc_mode) +{ + int status = CS_OK; + unsigned short saved_edc_mode = 0; + /* offset used for accessing host addresses over line ones */ + unsigned short reg_offset = 0x0000; + + /* init to disabled */ + *edc_mode = CS_HSIO_EDC_MODE_DISABLED; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + reg_offset = 0x0000; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE2PRELOAD0 + reg_offset, + &saved_edc_mode); + + switch (saved_edc_mode) { + /* Note, edc mode enum uses too many bits, hense the custom mapping here + * If the EDC version has never been initialized then the preloader will + * have the h/w reset value of 0xCCCC. Report this as EDC disabled + */ + case 0: + case 0xCCCC: + *edc_mode = CS_HSIO_EDC_MODE_DISABLED; + break; + case 1: + *edc_mode = CS_HSIO_EDC_MODE_CX1; + break; + case 2: + *edc_mode = CS_HSIO_EDC_MODE_SR; + break; + case 3: + *edc_mode = CS_HSIO_EDC_MODE_ZR; + break; + case 4: + *edc_mode = CS_HSIO_EDC_MODE_DWDM; + break; + case 5: + *edc_mode = CS_HSIO_EDC_MODE_10G_BP; + break; + case 6: + *edc_mode = CS_HSIO_EDC_MODE_15G_BP; + break; + case 7: + *edc_mode = CS_HSIO_EDC_MODE_5G_BP; + break; + case 8: + *edc_mode = CS_HSIO_EDC_MODE_7p5G_BP; + break; + case 9: + *edc_mode = CS_HSIO_EDC_MODE_8p5G_BP; + break; + case 10: + *edc_mode = CS_HSIO_EDC_MODE_FCAN; + break; + case 11: + *edc_mode = CS_HSIO_EDC_MODE_15G_BP_27dB; + break; + case 12: + *edc_mode = CS_HSIO_EDC_MODE_SMLRM; + break; + + default: + CS_TRACE(("ERROR: slice = %x, unknown saved EDC mode = %x\n", + slice, saved_edc_mode)); + status |= CS_ERROR; + break; + } + return status; +} + +int cs4224_init_edc_mode_intf(unsigned int slice, + struct cs4224_rules_t *rules, + enum e_cs4224_mseq_id intf) +{ + int status = CS_OK; + enum e_cs4224_edc_mode mode; + enum e_cs4224_trace_loss traceloss; + /* offset used for accessing host addresses over line ones */ + unsigned short reg_offset = 0x0000; + /* flags for fc or 8g apps */ + unsigned short reg_data = 0x0000; + + cs4224_lock(slice); + + if (cs4224_is_hw_simplex(slice)) { + mode = rules->rx_if.splx_edc_mode; + traceloss = rules->rx_if.splx_eq.traceloss; + + if (cs4224_line_rx_to_host_tx_dir(slice)) { + intf = CS4224_DPLX_LINE_MSEQ; + reg_offset = 0x0000; + } else { + intf = CS4224_DPLX_HOST_MSEQ; + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + } + } else if (cs4224_is_hw_duplex(slice)) { + if (intf == CS4224_DPLX_LINE_MSEQ) { + reg_offset = 0x0000; + + mode = rules->rx_if.dplx_line_edc_mode; + traceloss = rules->rx_if.dplx_line_eq.traceloss; + } else if (intf == CS4224_DPLX_HOST_MSEQ) { + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + mode = rules->rx_if.dplx_host_edc_mode; + traceloss = rules->rx_if.dplx_host_eq.traceloss; + } else { + CS_TRACE(("ERROR: Invalid interface. intf=%d\n", intf)); + return CS_ERROR; + } + } else { + /* error in the API checks for SKU... */ + CS_TRACE(("ERROR: unknown hardware id\n")); + return CS_ERROR; + } + + /* reset reset count */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_MSB + reg_offset, + 0x0000); + + /* Reset MSEQ datastore register between mode switches */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + reg_offset, + 0x803c); + + /* function number */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + reg_offset, + 0x800E); + + /* Reset some MSEQ registers to defaults between mode switches + * (may be overwritten below) + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4 + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_LSB + reg_offset, + 0x3000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_RESOLUTION + reg_offset, + 0x0001); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_LSB + reg_offset, + 0x0008); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_BIAS1 + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_BIAS1_dft); + + status |= cs4224_save_edc_mode(slice, reg_offset, mode); + + switch (mode) { + case CS_HSIO_EDC_MODE_SR: { + /* only set the SR bit, everything else is off by default */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + reg_offset, + 0x0001); + + /* set spare1[0] = 1 to speed up locking in SR mode */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_LSB + reg_offset, + 0x0001); + + /* power down is set differently from the scripts since spare12 + * is also different + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x0065); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB + reg_offset, + 0x0000); + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0003); + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x0099); + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1 + reg_offset, + 0x0004); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG + reg_offset, + 0x0441); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB + reg_offset, + 0xDFFF); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB + reg_offset, + 0x000D); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL + reg_offset, + 0x001E); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_OVERRIDE_EN + reg_offset, + 0x0000); + + /* function number set to 1 for SR only */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0 + reg_offset, + 0x0001); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + reg_offset, + 0x800E); + + /* apply pre-equalizer settings */ + status |= cs4224_update_pre_equalizer(slice, reg_offset, + traceloss); + + break; + } + + case CS_HSIO_EDC_MODE_CX1: + case CS_HSIO_EDC_MODE_SMLRM: { + /* differs from script, don't enable power savings or + * auto squelch by default + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + reg_offset, + 0x0B00); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB + reg_offset, + 0x0C09); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x001F); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x0099); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1 + reg_offset, + 0x0005); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB + reg_offset, + 0x8F00); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB + reg_offset, + 0x000c); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ1 + reg_offset, + 0x0008); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ2 + reg_offset, + 0x000B); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_LSB + reg_offset, + 0x00FF); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_MSB + reg_offset, + 0x0030); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_LSB + reg_offset, + 0x000F); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_LSB + reg_offset, + 0x2350); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_MSB + reg_offset, + 0x1650); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_MSB + reg_offset, + 0x07FF); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_LSB + reg_offset, + 0xFFFE); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_LSB + reg_offset, + 0x0010); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_MSB + reg_offset, + 0x0030); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_FLOAT + reg_offset, + 0x8001); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_LSB + reg_offset, + 0x001D); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_MSB + reg_offset, + 0x000A); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_LSB + reg_offset, + 0x3000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4 + reg_offset, + 0x85f0); + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_LSB + reg_offset, + 0x000A); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE0_1 + reg_offset, + 0x00F0); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE1_1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE2_1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE3_1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE4_1 + reg_offset, + 0x0000); + + /* Read efuse data (POLY_RES_CAL_DATAx) and configure + * itune/rtune settings + */ + if (intf == CS4224_DPLX_LINE_MSEQ) + status |= cs4224_pgm_reg_from_efuse( + slice, CS4224_CFG_LINE_SIDE); + else + status |= cs4224_pgm_reg_from_efuse( + slice, CS4224_CFG_HOST_SIDE); + + if (mode == CS_HSIO_EDC_MODE_CX1) { + /* the following sets the data slicer offset: + * 0x80 for CX1, 0x90 for ZR, DWDM TBD + */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_SLICER + + reg_offset, + 0x0080); + /* max PHASE_SELECT+1 */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB + + reg_offset, + 0x0023); + } else { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_SLICER + + reg_offset, + 0x0040); + /* max PHASE_SELECT+1 */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB + + reg_offset, + 0x0020); + } + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2 + reg_offset, + 0x0000); + + break; + } + + case CS_HSIO_EDC_MODE_DWDM: + case CS_HSIO_EDC_MODE_ZR: + case CS_HSIO_EDC_MODE_10G_BP: + case CS_HSIO_EDC_MODE_15G_BP: + case CS_HSIO_EDC_MODE_15G_BP_27dB: + case CS_HSIO_EDC_MODE_5G_BP: + case CS_HSIO_EDC_MODE_7p5G_BP: + case CS_HSIO_EDC_MODE_8p5G_BP: + printf("EDC Mode not supported\n"); + break; + case CS_HSIO_EDC_MODE_DISABLED: { + /* un-rail the driver charge pump current */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x0099); + + /* power everything up */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x001f); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x0000); + + /* un-squelch the driver */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH - reg_offset, + 0x0000); + + /* apply pre-equalizer settings */ + status |= cs4224_update_pre_equalizer(slice, reg_offset, + traceloss); + + break; + } + default: { + status |= cs4224_save_edc_mode(slice, reg_offset, + CS_HSIO_EDC_MODE_DISABLED); + + CS_TRACE( + ("ERROR: Invalid application mode %d.\n", mode)); + status |= CS_ERROR; + return status; + } + } + + /* if the ring oscillator VCO is used, override some of these values */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG + reg_offset, + ®_data); + if (reg_data & CS_BIT7) { + /* the ring oscillator requires the charge pump = 0x44 */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x0044); + + /* when using the ring oscillator, override srx_cml_rtune=0, + * srx_vco_itune=2 and srx_cml_itune=0 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE + reg_offset, + 0x0020); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE + reg_offset, + 0); + } + + cs4224_unlock(slice); + + return status; +} + +int cs4224_init_edc_mode_set(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (cs4224_is_hw_simplex(slice)) { + status |= cs4224_init_edc_mode_intf(slice, rules, + CS4224_SPLX_MSEQ); + } else if (cs4224_is_hw_duplex(slice)) { + if (rules->application != CS4224_TARGET_APPLICATION_FCAN) { + /* the FC-AN ucode configures the line side DFE mode, + * don't do it here... + */ + status |= cs4224_init_edc_mode_intf( + slice, rules, CS4224_DPLX_LINE_MSEQ); + } + status |= cs4224_init_edc_mode_intf(slice, rules, + CS4224_DPLX_HOST_MSEQ); + } else { + /* error in the API checks for SKU... */ + CS_TRACE(("ERROR: init_edc_mode_set: unknown hardware id")); + return CS_ERROR; + } + + return status; +} + +unsigned int cs4224_query_vco_rate(const struct cs4224_rules_t *rules) +{ + /* ref_clk_rate is in KHz */ + unsigned int ref_clk_rate = 0; + /* rdiv from clkdiv rules */ + unsigned int rdiv = 0; + /* calculated (approx) vco rate */ + unsigned int vco_rate = 0; + +#if defined(CS_HAS_FLOATING_POINT) + /* if we're using floating point then the ref_clk is in MHz, + * multiply up to get KHz and scrap the decimal + */ + ref_clk_rate = rules->ref_clk_rate * 1000; +#else + /* if we're not using floating point, then ref_clk_rate is in KHz */ + ref_clk_rate = rules->ref_clk_rate; +#endif + + /* decode clkdiv.rdiv for use in the calc */ + switch (rules->clkdiv.rdiv) { + case CS4224_RDIV_DIV64: + rdiv = 64; + break; + case CS4224_RDIV_DIV66: + rdiv = 66; + break; + case CS4224_RDIV_DIV80: + rdiv = 80; + break; + case CS4224_RDIV_DIV100: + rdiv = 100; + break; + case CS4224_RDIV_DIV128: + rdiv = 128; + break; + default: + /* doesn't matter,we might be out of range or using the FRACn */ + rdiv = 0; + break; + } + + if (rules->clkdiv.enable) { + /* we're just trying to find the VCO rate, not the data-rate, + * so ignore ddiv + */ + vco_rate = ref_clk_rate * rdiv; + } + + /* if using the clkdiv (for ddiv) AND the fracn, then this if statement + * must come last + */ + if (rules->fracdiv.enable) { + unsigned long long frac_part = + (unsigned long long)(ref_clk_rate) * + (rules->fracdiv.numerator); + /* decimate the 'fractional' part, left with int KHz */ + frac_part = frac_part >> 21; + vco_rate = (ref_clk_rate * 8 * rules->fracdiv.divisor) + + (unsigned int)frac_part; + } + + return vco_rate; +} + +unsigned int cs4224_query_data_rate(const struct cs4224_rules_t *rules) +{ + unsigned int vco_rate = cs4224_query_vco_rate(rules); + unsigned int data_rate = vco_rate; + + if (rules->clkdiv.enable) { + switch (rules->clkdiv.ddiv) { + case CS4224_RULE_DISABLED: + /* not sure how this happened, but ignore it */ + break; + default: + /* shift by the enum, since the divide + * amount == 2**(enum) + */ + data_rate = + vco_rate >> (unsigned short)(rules->clkdiv.ddiv); + break; + } + } + + return data_rate; +} + +unsigned char cs4224_need_low_lc_vco(const struct cs4224_rules_t *rules) +{ + unsigned int vco_rate = cs4224_query_vco_rate(rules); + + /* the 'real' range is 11.3G to 12.5G, but we'll fudge it a bit in case + * our fracn calcs have some rounding errors + */ + if ((vco_rate >= 11280000) && (vco_rate <= 12520000)) + return CS_TRUE; + + return CS_FALSE; +} + +int cs4224_force_low_lc_vco_intf(unsigned int slice, + enum e_cs4224_datapath_dir_t intf, + unsigned char force_enable) +{ + int status = CS_OK; + unsigned short offset = 0; + + if (intf == CS4224_LINE_RX_TO_HOST_TX_DIR) + offset = 0; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + if (force_enable) + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI + offset, + 0x40); + else + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI + offset, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI_dft); + + return status; +} + +int cs4224_force_and_init_low_lc_vco(unsigned int slice, + unsigned char force_enable) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_force_low_lc_vco_intf( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, force_enable); + status |= cs4224_init_vco( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_CONTROL); + } + + if (cs4224_is_hw_duplex(slice) || + (!cs4224_line_rx_to_host_tx_dir(slice))) { + status |= cs4224_force_low_lc_vco_intf( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, force_enable); + status |= cs4224_init_vco( + slice, CS4224_PP_HOST_SDS_COMMON_RXVCO0_CONTROL); + } + + return status; +} + +int cs4224_force_low_lc_vco(unsigned int slice, unsigned char force_enable) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_force_low_lc_vco_intf( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, force_enable); + } + + if (cs4224_is_hw_duplex(slice) || + (!cs4224_line_rx_to_host_tx_dir(slice))) { + status |= cs4224_force_low_lc_vco_intf( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, force_enable); + } + + return status; +} + +int cs4224_init_alt_coarse_tuning_intf(unsigned int slice, + enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short reg_data = 0; + unsigned short offset = 0x0000; + /* flag to say whether we should force the low lc vco or not */ + unsigned char force_low_lc_vco = CS_FALSE; + + status |= cs4224_get_cfg_side(slice, &intf); + if (status != CS_OK) + return status; + + cs4224_lock(slice); + + if (intf == CS4224_CFG_LINE_SIDE) { + offset = 0x0000; + } else if (intf == CS4224_CFG_HOST_SIDE) { + offset = CS4224_LINE_TO_HOST_OFFSET; + } else { + CS_TRACE(("ERROR: Invalid interface. intf=%d\n", intf)); + return CS_ERROR; + } + + /* level 4d00 is approx 77 deg C */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL3 + offset, + 0x4d00); + /* level 4100 is approx 65 deg C */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL2 + offset, + 0x4100); + /* level 3900 is approx 30 deg C */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL1 + offset, + 0x3900); + /* level 2d00 is approx 0 deg C */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL0 + offset, + 0x2d00); + + /* ring oscillator config reg */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG + offset, + ®_data); + + if (reg_data & CS_BIT7) { + /* if the 8G ring oscillator VCO is used */ + status |= cs4224_init_ro_vco_tmp_thresh(slice, intf); + } else { + /* the LC VCO */ + status |= cs4224_init_lc_vco_tmp_thresh(slice, intf); + + /* determine if we need to force the low LC VCO */ + force_low_lc_vco = cs4224_need_low_lc_vco(rules); + } + + status |= cs4224_force_low_lc_vco(slice, force_low_lc_vco); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_init_alt_coarse_tuning(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_init_alt_coarse_tuning_intf( + slice, CS4224_CFG_LINE_SIDE, rules); + } + if (cs4224_is_hw_duplex(slice) || !cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_init_alt_coarse_tuning_intf( + slice, CS4224_CFG_HOST_SIDE, rules); + } + + return status; +} + +int cs4224_disable_tx_driver_if_req(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + cs4224_lock(slice); + + /* Disable the transmitters if requested */ + if (cs4224_is_hw_simplex(slice)) { + if (cs4224_line_rx_to_host_tx_dir(slice) && + (rules->tx_if.splx_disable == CS_TRUE)) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, + 0x0800); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, + 0); + } + + if (!cs4224_line_rx_to_host_tx_dir(slice) && + (rules->tx_if.splx_disable == CS_TRUE)) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, + 0x0800); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, + 0); + } + } else { /* duplex */ + if (rules->tx_if.dplx_line_disable == CS_TRUE) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, + 0x0800); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, + 0); + } + if (rules->tx_if.dplx_host_disable == CS_TRUE) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, + 0x0800); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, + 0); + } + } + + cs4224_unlock(slice); + + return status; +} + +int cs4224_init_driver_trace_loss_intf( + unsigned int slice, + enum e_cs4224_datapath_dir_t intf, + enum e_cs4224_trace_loss trace_loss) +{ + int status = CS_OK; + unsigned short ctrla = 0; + unsigned short ctrlb = 0; + enum e_cs4224_tx_driver_interface driver; + + if (intf == CS4224_LINE_RX_TO_HOST_TX_DIR) { + driver = CS4224_TX_HOST_INTERFACE; + } else if (intf == CS4224_HOST_RX_TO_LINE_TX_DIR) { + driver = CS4224_TX_LINE_INTERFACE; + } else { + CS_TRACE(("ERROR: intf must be line or host, not simplex\n")); + return CS_ERROR; + } + + switch (trace_loss) { + case CS_HSIO_TRACE_LOSS_0dB: + case CS_HSIO_TRACE_LOSS_1dB: { + ctrla = 0x814; + ctrlb = 0x4; + break; + } + case CS_HSIO_TRACE_LOSS_2dB: { + ctrla = 0x3810; + ctrlb = 0x5; + break; + } + case CS_HSIO_TRACE_LOSS_3dB: { + ctrla = 0x4818; + ctrlb = 0x9; + break; + } + case CS_HSIO_TRACE_LOSS_4dB: { + ctrla = 0x4818; + ctrlb = 0xb; + break; + } + case CS_HSIO_TRACE_LOSS_5dB: { + ctrla = 0x4818; + ctrlb = 0xd; + break; + } + case CS_HSIO_TRACE_LOSS_6dB: { + ctrla = 0x4818; + ctrlb = 0xe; + break; + } + case CS_HSIO_TRACE_LOSS_15dB: { + ctrla = 0x782B; + ctrlb = 0x4; + break; + } + case CS_HSIO_TRACE_LOSS_27dB: { + ctrla = 0x7828; + ctrlb = 0x80A; + break; + } + case CS_HSIO_TRACE_LOSS_CR4: { + ctrla = 0x5827; + ctrlb = 0x6; + break; + } + case CS_HSIO_TRACE_LOSS_LAB: { + ctrla = 0x0813; + ctrlb = 0x1; + break; + } + default: { + CS_TRACE(("ERROR: Unsupported traceloss setting %d\n", + trace_loss)); + return CS_ERROR; + } + } + + status |= cs4224_init_driver_settings(slice, driver, ctrla, ctrlb); + + return status; +} + +int cs4224_init_mseq_dyn_reconfig_intf(unsigned int slice, + unsigned short offset) +{ + int status = CS_OK; + unsigned short reg_data; + + /* SPARE12[30] tells the DFE mission mode code mseq_dyn_reconfig is + * being used and to back to the mseq_dyn_reconfig code once each + * mission mode loop is done. + */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB + offset, + ®_data); + reg_data |= 0x4000; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB + offset, + reg_data); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_MSB + offset, + 0x4000); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_MSB + offset, + 0x4000); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB + offset, + 0x801e); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_MSB + offset, 0x0d80); + + return status; +} + +int cs4224_init_mseq_dyn_reconfig(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short reg_data; + + if ((rules->mseq_dyn_reconfig == CS_TRUE) && + (rules->application != CS4224_TARGET_APPLICATION_KRAN) && + (rules->application != CS4224_TARGET_APPLICATION_FCAN)) { + /* The mseq_dyn_reconfig feature is not compatible with + * the FC microcode + */ + status |= cs4224_reg_get_channel( + slice, CS4224_GLOBAL_UCODE_VERSION_KR, ®_data); + if (reg_data == 0) { + CS_TRACE(("ERROR: mseq_dyn_reconfig requires KR\n")); + return CS_ERROR; + } + + status |= cs4224_init_mseq_dyn_reconfig_intf(slice, 0); + status |= cs4224_init_mseq_dyn_reconfig_intf( + slice, CS4224_LINE_TO_HOST_OFFSET); + } + + return status; +} + +int cs4224_init_driver_trace_loss(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + enum e_cs4224_trace_loss host_traceloss, line_traceloss; + + if (cs4224_is_hw_simplex(slice)) { + host_traceloss = rules->tx_if.splx_driver.traceloss; + line_traceloss = rules->tx_if.splx_driver.traceloss; + } else { + host_traceloss = rules->tx_if.dplx_host_driver.traceloss; + line_traceloss = rules->tx_if.dplx_line_driver.traceloss; + } + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_init_driver_trace_loss_intf( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, host_traceloss); + } + + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_init_driver_trace_loss_intf( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, line_traceloss); + } + + return status; +} + +int cs4224_init_driver_settings(unsigned int slice, + enum e_cs4224_tx_driver_interface intf, + unsigned short ctrla, + unsigned short ctrlb) +{ + int status = CS_OK; + unsigned short offset = 0; + + if (cs4224_is_hw_simplex(slice) && + intf == CS4224_TX_SIMPLEX_INTERFACE) { + /* figure out which driver we need to change */ + if (cs4224_line_rx_to_host_tx_dir(slice)) + intf = CS4224_TX_HOST_INTERFACE; + else + intf = CS4224_TX_LINE_INTERFACE; + } else if (intf == CS4224_TX_SIMPLEX_INTERFACE) { + CS_TRACE(("ERROR: duplex slice cannot use intf = ")); + CS_TRACE(("CS4224_TX_SIMPLEX_INTERFACE\n")); + return CS_ERROR; + } + + if (intf == CS4224_TX_HOST_INTERFACE) + offset = CS4224_LINE_TO_HOST_OFFSET; + else + offset = 0; + + cs4224_lock(slice); + + /* update CTRLA/CTRLB registers */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA + offset, + ctrla); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB + offset, + ctrlb); + + cs4224_unlock(slice); + + return status; +} + +unsigned char cs4224_datarate_less_than_10G(struct cs4224_rules_t *rules) +{ + unsigned int data_rate = cs4224_query_data_rate(rules); + + if (data_rate < 10000000) + return CS_TRUE; + + return CS_FALSE; +} + +int cs4224_update_clkdiv_ctrl_intf(unsigned int slice, + enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short reg_data, old_data; + unsigned short offset = 0; + + status |= cs4224_get_cfg_side(slice, &intf); + if (status != CS_OK) + return status; + + if (intf == CS4224_CFG_LINE_SIDE) + offset = 0x0000; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL + offset, + ®_data); + old_data = reg_data; + + if (rules->clkdiv.enable) { + if (rules->clkdiv.rdiv != CS4224_RULE_DISABLED) { + reg_data &= ~0x000f; + reg_data |= rules->clkdiv.rdiv; + } + if (rules->clkdiv.ddiv != CS4224_RULE_DISABLED) { + reg_data &= ~0x0070; + reg_data |= (rules->clkdiv.ddiv << 4); + } + if (rules->clkdiv.fastdiv != CS4224_RULE_DISABLED) { + reg_data &= ~0xf000; + reg_data |= (rules->clkdiv.fastdiv << 12); + } + } else + /* Only time clkdiv rule is not enabled is when using the + * fracdiv without any integer divide (so ~10G rates, etc). + * In that case reset it to defaults. + * LINE dft == HOST dft + */ + reg_data = CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL_dft; + + if (old_data != reg_data) + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL + offset, + reg_data); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_update_clkdiv_ctrl(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_update_clkdiv_ctrl_intf( + slice, CS4224_CFG_LINE_SIDE, rules); + } + if (cs4224_is_hw_duplex(slice) || !cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_update_clkdiv_ctrl_intf( + slice, CS4224_CFG_HOST_SIDE, rules); + } + + return status; +} + +int cs4224_fracdiv_cdr_init(unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned short divisor, + unsigned int numerator) +{ + int status = CS_OK; + unsigned short reg_data, old_data; + + unsigned short frac0_reset_addr; + unsigned short clkdiv_ctrl_addr; + unsigned short frac0_width_addr; + unsigned short frac0_intdiv_addr; + unsigned short frac0_numerator0_addr; + unsigned short frac0_numerator1_addr; + unsigned short frac0_stage1preload0_addr; + unsigned short frac0_stage1preload1_addr; + unsigned short frac0_dither_addr; + unsigned short frac0_stage_en_addr; + unsigned short frac0_power_down_addr; + unsigned short mseq_options_addr; + unsigned short mseq_options; + enum e_cs4224_mseq_id mseq_id; + + /* sides and datapath_dir are the same enum */ + status |= cs4224_get_cfg_side(slice, &dir); + if (status != CS_OK) + return status; + + if (dir == CS4224_LINE_RX_TO_HOST_TX_DIR) { + frac0_reset_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_RESET; + clkdiv_ctrl_addr = + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL; + frac0_width_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_WIDTH; + frac0_intdiv_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_INTDIV; + frac0_numerator0_addr = + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR0; + frac0_numerator1_addr = + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR1; + frac0_stage1preload0_addr = + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0; + frac0_stage1preload1_addr = + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1; + frac0_dither_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_DITHER; + frac0_stage_en_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_STAGE_EN; + frac0_power_down_addr = + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB; + mseq_options_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW; + mseq_id = CS4224_DPLX_LINE_MSEQ; + } else { + frac0_reset_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_RESET; + clkdiv_ctrl_addr = + CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL; + frac0_width_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_WIDTH; + frac0_intdiv_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_INTDIV; + frac0_numerator0_addr = + CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR0; + frac0_numerator1_addr = + CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR1; + frac0_stage1preload0_addr = + CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0; + frac0_stage1preload1_addr = + CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1; + frac0_dither_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_DITHER; + frac0_stage_en_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_STAGE_EN; + frac0_power_down_addr = + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB; + mseq_options_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_SHADOW; + mseq_id = CS4224_DPLX_HOST_MSEQ; + } + + cs4224_lock(slice); + + /* find out if microsequencer is running */ + status |= cs4224_reg_get_channel(slice, mseq_options_addr, + &mseq_options); + + /* if microsequencer is running */ + if (0 == (0x0008 & mseq_options)) + /* stall the microsequencer */ + status |= cs4224_mseq_stall(slice, mseq_id, CS_TRUE); + + status |= cs4224_reg_get_channel(slice, frac0_power_down_addr, + ®_data); + old_data = reg_data; + reg_data &= ~0x0010; /* power-up FracN for configuration */ + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, frac0_power_down_addr, + reg_data); + + status |= cs4224_reg_get_channel(slice, frac0_reset_addr, ®_data); + old_data = reg_data; + reg_data &= ~0x0001; /* pull out of reset CDR fracn */ + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, frac0_reset_addr, + reg_data); + + status |= cs4224_reg_get_channel(slice, clkdiv_ctrl_addr, ®_data); + old_data = reg_data; + reg_data &= ~0x000f; + reg_data |= 0x9; /* Set the RDIV_SEL field to Fractional-N */ + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, clkdiv_ctrl_addr, + reg_data); + + status |= cs4224_reg_get_channel(slice, frac0_width_addr, ®_data); + old_data = reg_data; + reg_data &= ~0x0003; /* Setup to use a 24 bit accumulator */ + reg_data |= CS4224_FRACDIV_ACCUM_WIDTH_24BIT; + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, frac0_width_addr, + reg_data); + + status |= cs4224_reg_get_channel(slice, frac0_intdiv_addr, ®_data); + old_data = reg_data; + reg_data &= ~0x00ff; + reg_data |= (divisor & 0xff); /* Configure the denominator value */ + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, frac0_intdiv_addr, + reg_data); + + /* Configure the numerator value */ + status |= cs4224_reg_set_channel(slice, frac0_numerator0_addr, + numerator & 0xFFFF); + status |= cs4224_reg_set_channel(slice, frac0_numerator1_addr, + (numerator >> 16) & 0xFF); + + /* Configure the stage 1 preload value */ + status |= cs4224_reg_set_channel(slice, frac0_stage1preload0_addr, + 0x5DC6); + status |= cs4224_reg_set_channel(slice, frac0_stage1preload1_addr, + 0x0034); + + status |= cs4224_reg_set_channel(slice, frac0_dither_addr, 0x0000); + + /* Enable stage1 only */ + status |= cs4224_reg_set_channel(slice, frac0_stage_en_addr, 0x0408); + + status |= cs4224_reg_get_channel(slice, frac0_reset_addr, ®_data); + reg_data |= 0x0001; /* reset CDR fracn */ + status |= cs4224_reg_set_channel(slice, frac0_reset_addr, reg_data); + reg_data &= ~0x0001; /* pull out of reset CDR fracn */ + status |= cs4224_reg_set_channel(slice, frac0_reset_addr, reg_data); + + /* if microsequencer was running */ + if (0 == (0x0008 & mseq_options)) { + /* un-stall the microsequencer */ + status |= cs4224_mseq_stall(slice, mseq_id, CS_FALSE); + } + + cs4224_unlock(slice); + + return status; +} + +int cs4224_update_cdr_fracn(unsigned int slice, struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (rules->fracdiv.enable) { + /* enable the fractional divider */ + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_fracdiv_cdr_init( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, + rules->fracdiv.divisor, + rules->fracdiv.numerator); + } + + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_fracdiv_cdr_init( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, + rules->fracdiv.divisor, + rules->fracdiv.numerator); + } + } + /* clkdiv rdiv will control the use of the fracn, so we never have to + * reset the fracn settings as long as the clkdiv is re-programmed + */ + + return status; +} + +int cs4224_restore_powered_down_regs(unsigned int slice) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_MISC, + CS4224_PP_HOST_SDS_COMMON_STX0_MISC_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG, + CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG, + CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft); + } + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_MISC, + CS4224_PP_LINE_SDS_COMMON_STX0_MISC_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1, + CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG, + CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB, + CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB, + CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG, + CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG, + CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft); + } + return status; +} + +int cs4224_slice_power_down(unsigned int slice) +{ + int status = CS_OK; + + if ((cs4224_is_hw_simplex(slice) && + cs4224_line_rx_to_host_tx_dir(slice)) || + (cs4224_is_hw_duplex(slice))) { + /* stall the microsequencer */ + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_LINE_MSEQ, CS_TRUE); + + /* STX_PD=1, STX_PD_MUX=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_MISC, 0x8033); + /* SRX_AGC_ENB_LIMAMP=0 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1, + 0x0004); + /* SRX_DFE_BYPASS_EN=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG, + 0x0441); + /* SRX_DAC_ENB<19:0>=0xfffff */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB, + 0xffff); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB, + 0x000f); + /* SRX_AMP_PD=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG, + 0x0044); + /* SRX_VCO_EN=0, SRX_VCO_PDMUX_EN=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG, + 0x0705); + /* SRX_CLKDIV_PD=1, SRX_PD_DEMUX=7 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x03ff); + } + if ((cs4224_is_hw_simplex(slice) && + !cs4224_line_rx_to_host_tx_dir(slice)) || + (cs4224_is_hw_duplex(slice))) { + /* stall the microsequencer */ + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_HOST_MSEQ, CS_TRUE); + + /* STX_PD=1, STX_PD_MUX=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_MISC, 0x8033); + /* SRX_AGC_ENB_LIMAMP=0 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1, + 0x0004); + /* SRX_DFE_BYPASS_EN=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG, + 0x0441); + /* SRX_DAC_ENB<19:0>=0xfffff */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB, + 0xffff); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB, + 0x000f); + /* SRX_AMP_PD=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG, + 0x0044); + /* SRX_VCO_EN=0, SRX_VCO_PDMUX_EN=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG, + 0x0705); + /* SRX_CLKDIV_PD=1, SRX_PD_DEMUX=7 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x03ff); + } + + return status; +} + +int cs4224_apply_workarounds_power_down(unsigned int die) +{ + int status = CS_OK; + unsigned short data; + + cs4224_lock(die); + + /* get scratch 6 value from die to determine if we have already applied + * workarounds + */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + if (CS_IF_SET(data, CS_BIT0)) + /* workarounds already applied, bail out. */ + return CS_OK; + + /* make sure the mseqs are stalled, can't use broadcast otherwise! */ + status |= cs4224_reg_get( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW, &data); + if (CS_IF_CLR(data, CS_BIT3)) { + CS_TRACE(("ERROR: MSEQs on die 0x%x are not stalled.\n" + "This method is being used incorrectly.\n", die)); + return CS_ERROR; + } + + /* Apply workarounds to all port-pairs on the die, Bugzilla #37471 */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + { + /* power-down all slices as per Bug #38832 */ + /* STX_PD=1, STX_PD_MUX=1 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_STX0_MISC, 0x8033); + /* SRX_AGC_ENB_LIMAMP=0 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1, + 0x0004); + /* SRX_DFE_BYPASS_EN=1 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG, 0x0441); + /* SRX_DAC_ENB<19:0>=0xfffff */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB, + 0xffff); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB, + 0x000f); + /* SRX_AMP_PD=1 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG, 0x0044); + /* SRX_VCO_EN=0, SRX_VCO_PDMUX_EN=1 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG, 0x0705); + /* SRX_CLKDIV_PD=1, SRX_PD_DEMUX=7 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x03ff); + } + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + + /* Mark all of the workarounds as complete */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + status |= cs4224_reg_set(die, CS4224_GLOBAL_SCRATCH6, + CS_SET(data, CS_BIT0)); + + cs4224_unlock(die); + + return status; +} + +int cs4224_slice_soft_reset_intf(unsigned int slice, + enum e_cs4224_cfg_sides_t intf) +{ + int status = CS_OK; + int tmp_status = CS_OK; + unsigned short data = 0; + unsigned short reg_offset = 0; + enum e_cs4224_mseq_id mseq_id = CS4224_DPLX_LINE_MSEQ; + enum e_cs4224_mseq_id other_mseq_id = CS4224_DPLX_HOST_MSEQ; + unsigned int mate_slice = 0xFF; + unsigned char stalled = CS_FALSE; + unsigned char power_savings = CS_FALSE; + unsigned short other_power_down = 0x0; + + if (intf == CS4224_CFG_LINE_SIDE) { + reg_offset = 0; + mseq_id = CS4224_DPLX_LINE_MSEQ; + other_mseq_id = CS4224_DPLX_HOST_MSEQ; + } else if (intf == CS4224_CFG_HOST_SIDE) { + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + mseq_id = CS4224_DPLX_HOST_MSEQ; + other_mseq_id = CS4224_DPLX_LINE_MSEQ; + } else { + CS_TRACE(("ERROR: intf must be line/host, not splx. intf=%d\n", + intf)); + return CS_ERROR; + } + + /* make sure mseq is stalled on this interface, if not, then stall and + * don't unstall after the reset + */ + status |= cs4224_query_mseq_is_stalled(slice, mseq_id, &stalled); + if (!stalled) + status |= cs4224_mseq_stall(slice, mseq_id, CS_TRUE); + + /* we need to control the power_down on both line and host interfaces. + * In simplex, the other interface's mseq may be running, so turn off + * power savings so we can mess around with power_down without affecting + * traffic + */ + tmp_status |= cs4224_simplex_mate_slice(slice, &mate_slice); + if ((mate_slice & 0xFF) == 0xFF) { + /* doesn't have a mate slice, which means the other slice is not + * configured nor running + */ + power_savings = CS_FALSE; + } else if (tmp_status != CS_OK) { + /* some other kind of error, not good */ + CS_TRACE(("ERROR getting mate slice\n")); + status |= tmp_status; + } else { + /* we do have a mate slice, or on duplex it's the same slice, + * either way check power savings + */ + status |= cs4224_query_mseq_power_savings(mate_slice, + other_mseq_id, + &power_savings); + if (power_savings) + status |= cs4224_mseq_enable_power_savings( + mate_slice, other_mseq_id, CS_FALSE); + } + + if (status != CS_OK) + return status; + + cs4224_lock(slice); + + /* clock and power up everything */ + if (intf == CS4224_CFG_LINE_SIDE) { + /* only touch Rx stuff */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, &data); + data |= 0x00ff; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, data); + + /* host-side reg doesn't have Tx settings */ + } else { + /* only touch Rx stuff */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_HOSTMISC_CLKEN, 0x0041); + + /* only touch Tx stuff on the other side */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, &data); + data |= 0xff00; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, data); + } + + /* save the other-side's power down so we can restore it later */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB - reg_offset, + &other_power_down); + + /* stagger power up */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x001F); + /* stagger power up only if we won't kill anything, this works because + * if it's already on (cleared to 0) then this won't turn it off trying + * to write 0x1F into the reg + * NOTE: There is an issue (maybe?) in the PRBS checker that when you + * clear bit6 you will get a momenary loss of PRBS sync this does not + * effect traffic through the device, only the PRBS checker + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB - reg_offset, + (other_power_down & 0x001F)); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB - reg_offset, + 0x0000); + + /* reset most of the Rx settings */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_SOFT_RESET + reg_offset, 0x0031); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG + reg_offset, + 0x0003); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_SOFT_RESET + reg_offset, 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG + reg_offset, + 0x0000); + + /* some stuff isn't hit by those resets, so reset those manually */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_CONTROL + reg_offset, + CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_CONTROL_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RX0_Config + reg_offset, + CS4224_PP_LINE_SDS_COMMON_RX0_Config_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXELST0_Control + reg_offset, + CS4224_PP_LINE_SDS_COMMON_RXELST0_Control_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKOUT_CTRL + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKOUT_CTRL_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_MONCTRL + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_MONCTRL_dft); + + /* RX_CONFIG on the RX side has a Tx side Tx bit for some reason. + * Yes this register is correct, so the LINE_SDRX0_RX_CONFIG + * will contain the analog host Tx polarity inversion bit + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_dft); + + /* Reset some Tx registers that weren't hit by the Rx soft reset + * These are mostly just registers not touched by + * cs4224_slice_enter_operational_state + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_TX0_Config - reg_offset, + CS4224_PP_HOST_SDS_COMMON_TX0_Config_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_TXELST0_Control - reg_offset, + CS4224_PP_HOST_SDS_COMMON_TXELST0_Control_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_CONFIG - reg_offset, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE - reg_offset, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE - reg_offset, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_MISC - reg_offset, + CS4224_PP_HOST_SDS_COMMON_STX0_MISC_dft); + + /* Reset some stuff that's normally reset in + * cs4224_restore_powered_down_regs + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG_dft); + + /* Unfortunately the soft reset wipes out the per-port workarounds on + * this slice, so re-apply them + * NOTE: Sync this block of writes with those in the + * cs4224_apply_workarounds method + */ + + /* Adjust the LC-VCO bias current because the defaults are wrong. + * See bugzilla #36619,39270 for details + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_VCOBIAS + reg_offset, + 0x0907); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL00 + reg_offset, + 0x3222); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL01 + reg_offset, + 0x4444); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL02 + reg_offset, + 0x5555); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL03 + reg_offset, + 0x6666); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL10 + reg_offset, + 0x7654); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL11 + reg_offset, + 0x8877); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL12 + reg_offset, + 0xa999); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL13 + reg_offset, + 0xccba); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL + reg_offset, + 0x001e); + + /* clear bit 13 (bug 37471) */ + data = CS_CLR(CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE_dft, CS_BIT13); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE + reg_offset, + data); + + /* clear common_tx_sr reset */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_SOFT_RESET + reg_offset, + 0x0000); + + /* force driver charge pump high to eliminate cross-talk */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x80dd); + + /* DATAPATH_CTRL is different between line and host, but the + * host bits that are different are reserved so it doesn't + * matter if we try to write them + */ + data = CS_SET(CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL_dft, CS_BIT1); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL + reg_offset, + data); + + /* Reset power-down and clken before proceeding */ + if (intf == CS4224_CFG_LINE_SIDE) { + /* reset Rx stuff */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, &data); + data &= 0xff00; + data |= 0x0060; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, data); + /* no Tx stuff in host reg */ + } else { + /* reset Rx stuff */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_HOSTMISC_CLKEN, 0x0000); + + /* reset Tx stuff on other side */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, &data); + data &= 0x00ff; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, data); + } + + /* set power down to default on this interface */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft); + + if (!power_savings) { + /* restore power down on the other interface */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB - reg_offset, + other_power_down); + } + + cs4224_unlock(slice); + + /* re-enable power savings on the other interface if needed */ + if (power_savings) { + status |= cs4224_mseq_enable_power_savings(mate_slice, + other_mseq_id, + CS_TRUE); + } + + return status; +} + +int cs4224_slice_soft_reset(unsigned int slice) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_slice_soft_reset_intf(slice, + CS4224_CFG_LINE_SIDE); + } + if (cs4224_is_hw_duplex(slice) || !cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_slice_soft_reset_intf(slice, + CS4224_CFG_HOST_SIDE); + } + + return status; +} + +int cs4224_apply_workarounds(unsigned int die) +{ + int status = CS_OK; + unsigned short data; + + cs4224_lock(die); + + /* scratch6 value determines if we have already applied workarounds */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + if (CS_IF_SET(data, CS_BIT0)) { + /* workarounds already applied, bail out. */ + return CS_OK; + } + + /* make sure the mseqs are stalled, can't use broadcast otherwise! */ + status |= cs4224_reg_get( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW, &data); + if (CS_IF_CLR(data, CS_BIT3)) { + CS_TRACE(("ERROR: MSEQs on die 0x%x are not stalled.\n" + "This method is being used incorrectly.\n", die)); + return CS_ERROR; + } + + /* At this point, the device is essentially right out of reset */ + + /* Change the temperature and voltage monitors to poll */ + status |= cs4224_enable_monitor_sense_points(die, CS_FALSE); + + /* Increase MDIO timeout as per Bugzilla 35875 */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_MDIO_CONFIG, + CS4224_GLOBAL_MDIO_CONFIG_pref); + + /* load the 0.9v monitor calibration constant */ + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_MON_GAIN_DATA, &data); + status |= cs4224_reg_set(die, CS4224_MONITOR_CAL_OVERRIDE, data); + + /* load the 1.8v monitor calibration constant */ + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_MON_LUT15, &data); + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_VALUE0, data); + + /* make use of the temperature and 0.9v voltage calibration constants */ + status |= cs4224_reg_set(die, CS4224_MONITOR_CAL_CONST_OVERRIDE_ENA, + 0x0004); + status |= cs4224_reg_set(die, CS4224_MONITOR_CAL_CONST_APPLY, 0x0005); + + /* make use of the 1.8v voltage calibration constant */ + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_RANGE0, 0xffff); + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_SELECT, 0x0000); + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_LOCAL_SELECT, 0x0040); + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_APPLY, 0x0040); + + /* Apply workarounds to all port-pairs (PP) on the die */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + + /* Adjust the LC-VCO bias current because the defaults are wrong. + * See bugzilla #36619,39270 for details + * NOTE: Sync these values with those in the cs4224_slice_soft_reset + * method + */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_VCOBIAS, + 0x0907); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL00, + 0x3222); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL01, + 0x4444); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL02, + 0x5555); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL03, + 0x6666); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL10, + 0x7654); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL11, + 0x8877); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL12, + 0xa999); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL13, + 0xccba); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL, 0x001e); + + /* clear bit 13 (bug 37471) */ + data = CS_CLR(CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE_dft, CS_BIT13); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE, data); + + /* clear common_tx_sr reset */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_SOFT_RESET, 0x0); + + /* force driver charge pump high to eliminate cross-talk */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA, 0x80dd); + + /* DATAPATH_CTRL is different between line and host, but the + * host bits that are different are reserved so it doesn't + * matter if we try to write them + */ + data = CS_SET(CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL_dft, + CS_BIT1); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL, data); + + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + + cs4224_unlock(die); + + return status; +} + +int cs4224_apply_post_ucode_dwld_workarounds(unsigned int die) +{ + int status = CS_OK; + unsigned short data; + + cs4224_lock(die); + + /* make sure the mseqs are stalled, can't use broadcast otherwise! */ + status |= cs4224_reg_get( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW, &data); + if (CS_IF_CLR(data, CS_BIT3)) { + CS_TRACE(("ERROR: MSEQs on die 0x%x are not stalled.\n" + "This method is being used incorrectly.\n", die)); + return CS_ERROR; + } + + /* Apply workarounds to all port-pairs on the die, Bugzilla #37471 */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + + /* force driver charge pump high (to rail) to elimitnate cross-talk */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA, 0x80dd); + + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + + cs4224_unlock(die); + + return status; +} + +int cs4224_dump_debug_info(unsigned int slice, struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + const char *app = cs4224_translate_app_mode(rules->application); + const char *edc_mode; + const char *edc_mode2; + + char data_rate_str[15] = ""; + + if (rules->application == CS4224_TARGET_APPLICATION_KRAN) + CS_SNPRINTF((data_rate_str, + ARRAY_SIZE(data_rate_str), + "0x%04x", + rules->kran.data_rates)); + else + CS_SNPRINTF((data_rate_str, + ARRAY_SIZE(data_rate_str), + "%uMbps", + (cs4224_query_data_rate(rules) / 1000))); + + if (cs4224_is_hw_simplex(slice)) { + edc_mode = + cs4224_translate_edc_mode(rules->rx_if.splx_edc_mode); + edc_mode2 = edc_mode; + } else { + edc_mode = cs4224_translate_edc_mode( + rules->rx_if.dplx_line_edc_mode); + edc_mode2 = cs4224_translate_edc_mode( + rules->rx_if.dplx_host_edc_mode); + } + + switch (hw_id) { + case CS4224_HW_CS4223: /* 4 port duplex */ + CS_PRINTF(("\nK2 configured for Duplex CS4223,Max ports = %d\n", + cs4224_max_num_ports)); + CS_PRINTF(("slice = %x, die = %x, PP offset = 0x%05x\n", + slice & 0xff, + cs4224_get_die_from_slice(slice), + cs4224_adj_pp(slice, 0))); + CS_PRINTF(("application = %s, data rate = %s, ", + app, data_rate_str)); + CS_PRINTF(("line edc_mode = %s, host edc_mode = %s\n", + edc_mode, edc_mode2)); + + break; + + case CS4224_HW_CS4224: /* 16 port simplex */ + case CS4224_HW_CS4343: /* 8 port duplex */ + case CS4224_HW_CS4221: /* 10 port simplex */ + case CS4224_HW_CS4227: /* 2 port duplex */ + case CS4224_HW_CS4210: /* 16 port simplex */ + case CS4224_HW_CS4341: /* 8 port duplex */ + status = CS_ERROR; + printf("SKU not yet supported !\n"); + break; + default: + CS_PRINTF(("\nERROR: K2 Efuse SKU not configured\n\n")); + status = CS_ERROR; + + break; + } + + return status; +} + +unsigned char cs4224_is_eeprom_finished(unsigned int die) +{ + unsigned short efuse_general_status; + unsigned short global_pin_status; + unsigned short eeprom_loader_status; + + cs4224_reg_get(die, CS4224_EFUSE_GENERAL_STATUS, &efuse_general_status); + if (efuse_general_status != 0x0001) { + /* EFUSE has not finished loading */ + return CS_FALSE; + } + + cs4224_reg_get(die, CS4224_GLOBAL_PIN_STATUS, &global_pin_status); + /* 0xf00d means the eeprom loader is still running + * 0xffff means the refclk isn't stable + */ + if (global_pin_status == 0xf00d || + global_pin_status == 0xffff || + global_pin_status == 0xbada) { + return CS_FALSE; + } else if ((global_pin_status & 0x4000) == 0) + /* EEPROM not present */ + return CS_TRUE; + + cs4224_reg_get(die, CS4224_EEPROM_LOADER_STATUS, &eeprom_loader_status); + if (eeprom_loader_status == 0xbada) + return CS_FALSE; + + if ((eeprom_loader_status & 0x0007) != 0) + /* EEPROM load abort, load failed, or load done */ + return CS_TRUE; + + return CS_FALSE; +} + +int cs4224_wait_for_eeprom_finished( + unsigned int die, unsigned int max_iterations, + unsigned int ms_delay_between_iterations) +{ + int status = CS_OK; + unsigned char finished = CS_FALSE; + unsigned int attempt = 0; + + do { + finished = cs4224_is_eeprom_finished(die); + + if (!finished) { + if (ms_delay_between_iterations == 0) + CS_MDELAY(1); + else + CS_MDELAY(ms_delay_between_iterations); + } + } while ((attempt++ < max_iterations) && (finished == CS_FALSE)); + + if (finished == CS_TRUE) { + status = CS_OK; + } else { + CS_TRACE(("ERROR: EEPROM not loading, die=%x\n", die)); + status = CS_ERROR; + } + + return status; +} + +int cs4224_update_scratch_regs(unsigned int slice) +{ + int status = CS_OK; + unsigned short reg_addr = 0x0; + unsigned short inc = 0x0; + unsigned short counter = 0x0; + unsigned char local_slice = slice & 0xff; + + /* which scratch you use is based off of the PP, + * ex PP2 is GLOBAL_SCRATCH2 + */ + reg_addr = CS4224_GLOBAL_SCRATCH0 + (cs4224_adj_pp(slice, 0x0) >> 12); + + /* increment is based off of the die, ex slice 2 is die 1 which is the + * upper bits of GLOBAL_SCRATCH2, so inc will be 0x0100. + * See global_scratch_allocation.txt for more info + */ + inc = (cs4224_get_die_from_slice(local_slice) == 1) ? 0x0100 : 0x0001; + + cs4224_lock(slice); + + status |= cs4224_reg_get_channel(slice, reg_addr, &counter); + counter += inc; + status |= cs4224_reg_set_channel(slice, reg_addr, counter); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_check_rules(unsigned int slice, struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned char bad_state = CS_FALSE; + unsigned short valid_edc_modes = 0; + + switch (rules->application) { + case CS4224_TARGET_APPLICATION_OC12: + case CS4224_TARGET_APPLICATION_1G: + case CS4224_TARGET_APPLICATION_1G_FC: + case CS4224_TARGET_APPLICATION_2G_FC: + case CS4224_TARGET_APPLICATION_4G_FC: + case CS4224_TARGET_APPLICATION_5G: + case CS4224_TARGET_APPLICATION_7p5G: + case CS4224_TARGET_APPLICATION_8G_FC: + case CS4224_TARGET_APPLICATION_16G_FC: + case CS4224_TARGET_APPLICATION_15G: + case CS4224_TARGET_APPLICATION_10G_KR: + case CS4224_TARGET_APPLICATION_40G_KR: + case CS4224_TARGET_APPLICATION_KRAN: + case CS4224_TARGET_APPLICATION_FCAN: + case CS4224_TARGET_APPLICATION_8G: + case CS4224_TARGET_APPLICATION_8p5G: + case CS4224_TARGET_APPLICATION_10G_FC: + printf("Target application mode not yet supported!\n"); + status = CS_ERROR; + break; + case CS4224_TARGET_APPLICATION_10G: { + valid_edc_modes = + CS_HSIO_EDC_MODE_SR | + CS_HSIO_EDC_MODE_10G_BP | + CS_HSIO_EDC_MODE_CX1 | + CS_HSIO_EDC_MODE_SMLRM | + CS_HSIO_EDC_MODE_DWDM | + CS_HSIO_EDC_MODE_ZR; + + if (cs4224_is_hw_simplex(slice)) + bad_state = + !(rules->rx_if.splx_edc_mode & valid_edc_modes); + else + bad_state = + !((rules->rx_if.dplx_host_edc_mode & + valid_edc_modes) && + (rules->rx_if.dplx_line_edc_mode & + valid_edc_modes)); + + if (bad_state) { + CS_TRACE(("ERROR: target app only supports EDC modes")); + CS_TRACE(("SR, CX1, 10G_BP, DWDM, and ZR\n")); + status |= CS_ERROR; + } + break; + } + } + + /* validate simplex/duplex rules */ + if (cs4224_is_hw_simplex(slice)) { + /* These traceloss settings are for the driver only */ + bad_state = + rules->rx_if.splx_eq.traceloss == + CS_HSIO_TRACE_LOSS_CR4 || + rules->rx_if.splx_eq.traceloss == + CS_HSIO_TRACE_LOSS_27dB || + rules->rx_if.splx_eq.traceloss == + CS_HSIO_TRACE_LOSS_15dB || + rules->rx_if.splx_eq.traceloss == + CS_HSIO_TRACE_LOSS_LAB; + if (bad_state) { + CS_TRACE(("ERROR: Traceloss settings of 15/27dB or ")); + CS_TRACE(("CR4/LAB are for the tx_if.*_driver.")); + CS_TRACE(("traceloss setting only.\n")); + status |= CS_ERROR; + } + + /* FEC available for simplex parts only */ + bad_state = rules->enable_fec; + if (bad_state) { + CS_TRACE(("ERROR: FEC not supported on simplex\n")); + status |= CS_ERROR; + } + } else { + /* These traceloss settings are for the driver only */ + bad_state = + rules->rx_if.dplx_host_eq.traceloss == + CS_HSIO_TRACE_LOSS_15dB || + rules->rx_if.dplx_host_eq.traceloss == + CS_HSIO_TRACE_LOSS_27dB || + rules->rx_if.dplx_host_eq.traceloss == + CS_HSIO_TRACE_LOSS_CR4 || + rules->rx_if.dplx_host_eq.traceloss == + CS_HSIO_TRACE_LOSS_LAB || + rules->rx_if.dplx_line_eq.traceloss == + CS_HSIO_TRACE_LOSS_15dB || + rules->rx_if.dplx_line_eq.traceloss == + CS_HSIO_TRACE_LOSS_27dB || + rules->rx_if.dplx_line_eq.traceloss == + CS_HSIO_TRACE_LOSS_CR4 || + rules->rx_if.dplx_line_eq.traceloss == + CS_HSIO_TRACE_LOSS_LAB; + if (bad_state) { + CS_TRACE(("ERROR: Traceloss settings of 15/27dB or ")); + CS_TRACE(("CR4/LAB are for the tx_if.*_driver.")); + CS_TRACE(("traceloss setting only.\n")); + status |= CS_ERROR; + } + } + + /* validate the refclk is correct */ + if ((rules->ref_clk_rate > 180000) || (rules->ref_clk_rate < 50000)) { + /* ref clk can only be 50-180MHz */ + CS_TRACE(("ERROR: ref_clk_rate is the internal reference ")); + CS_TRACE(("clock rate, which can only be between 50MHz and ")); + CS_TRACE(("180MHz\nIf you are using the REFDIV2_ENB pin then")); + CS_TRACE((" div your refclk by 2 for the ref_clk_rate val\n")); + status |= CS_ERROR; + } + + if (status != CS_OK) + CS_TRACE(("ERROR: bad rules config on slice %x\n", slice)); + + return status; +} + +int cs4224_manage_ucode_download(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + unsigned short timestamp[2] = { 0xffff, 0xffff }; + unsigned short yyyy, mmdd, hhmm; + unsigned int die, other_die; + unsigned char die_broadcast = CS_FALSE; + unsigned short version_kr, version_fc; + unsigned short *ucode_image = NULL; + unsigned int size_image = 0; + unsigned char stalled = CS_FALSE; + enum e_cs4224_ucode_image required_image = CS4224_UCODE_IMAGE_ANY; + enum e_cs4224_ucode_image loaded_image = CS4224_UCODE_IMAGE_NONE; + + /* die being programmed */ + die = cs4224_get_die_from_slice(slice); + /* the other die */ + other_die = die ^ 0x1; + + cs4224_lock(slice); + + /* Check to see if the microcode has already been programmed */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_TIMESTAMP0, + ×tamp[0]); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_VERSION_KR, + &version_kr); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_VERSION_FC, + &version_fc); + + if (cs4224_max_num_dies == 2) { + status |= cs4224_reg_get(other_die, + CS4224_GLOBAL_UCODE_TIMESTAMP0, + ×tamp[1]); + } + cs4224_unlock(slice); + + /* decide if we should broadcast ucode to both dies */ + if (rules->enable_die_broadcast && + (cs4224_max_num_dies == 2) && + (timestamp[0] == 0) && + (timestamp[1] == 0)) + die_broadcast = CS_TRUE; + + /* apply die workarounds, if necessary */ + status |= cs4224_apply_workarounds(die); + if (die_broadcast) + status |= cs4224_apply_workarounds(other_die); + + if (status != CS_OK) + return status; + + /* determine what our microcode requirements are */ + if (rules->application == CS4224_TARGET_APPLICATION_KRAN) + required_image = CS4224_UCODE_IMAGE_KR; + else if (rules->application == CS4224_TARGET_APPLICATION_FCAN) + required_image = CS4224_UCODE_IMAGE_FC; + + /* determine what is currently loaded */ + if (version_kr != 0) + loaded_image = CS4224_UCODE_IMAGE_KR; + else if (version_fc != 0) + loaded_image = CS4224_UCODE_IMAGE_FC; + + /* if the currently loaded ucode is not what we need */ + if ((loaded_image & required_image) == 0) { + if (required_image != CS4224_UCODE_IMAGE_FC) { + ucode_image = cs4224_kr_ucode_image; + size_image = sizeof(cs4224_kr_ucode_image) + / sizeof(unsigned short); + } + + if (die_broadcast) { + CS_PRINTF(("Broadcasting image\n")); + /* broadcast to both dies */ + status |= cs4224_ucode_data_prgm_image_broadcast( + slice, ucode_image, size_image); + } else { /* unicast */ + CS_PRINTF(("Unicasting image\n")); + /* only broadcast to single die */ + status |= cs4224_ucode_data_prgm_image(slice, + ucode_image, + size_image); + } + + /* check that the ucode programmed correctly */ + if (status != CS_OK) { + CS_TRACE(("ERROR downloading microcode, exiting\n")); + return status; + } + + /* check if post-setup in the ucode image unstalled the mseqs + * (it shouldn't). Note you can check any mseq on this die, + * since they should all be configured equally + */ + status |= cs4224_query_mseq_is_stalled(slice, + CS4224_DPLX_LINE_MSEQ, + &stalled); + if (!stalled) { + /* Iterate over all the slices on this die */ + unsigned int first_slice = 0; + unsigned int last_slice = 0; + unsigned int mid_slice = + CS4224_MAX_NUM_SLICES(slice) / 2; + unsigned int upper_bits = slice & 0xffffff00; + unsigned char i = 0; + unsigned int slice_i = 0; + + if (die_broadcast || CS4224_MAX_NUM_DIES(slice) == 1) { + /* reset all the slices */ + first_slice = 0; + last_slice = CS4224_MAX_NUM_SLICES(slice) - 1; + } else { + /* only reset mseqs on this die */ + if (slice < mid_slice) { + first_slice = 0; + last_slice = mid_slice - 1; + } else { + first_slice = mid_slice; + last_slice = CS4224_MAX_NUM_SLICES( + slice) + - 1; + } + } + + for (i = first_slice; i <= last_slice; i++) { + slice_i = upper_bits | i; + + /* stall the microsequencer(s) again */ + if (cs4224_is_hw_simplex(slice_i)) { + status |= cs4224_mseq_stall( + slice_i, CS4224_SPLX_MSEQ, + CS_TRUE); + } else { + status |= cs4224_mseq_stall( + slice_i, CS4224_DPLX_LINE_MSEQ, + CS_TRUE); + status |= cs4224_mseq_stall( + slice_i, CS4224_DPLX_HOST_MSEQ, + CS_TRUE); + } + } + } /* stall mseq block */ + + /* re-apply some die workarounds that got removed in the ucode + * download + */ + status |= cs4224_apply_post_ucode_dwld_workarounds(die); + if (die_broadcast) + status |= cs4224_apply_post_ucode_dwld_workarounds( + other_die); + } /* pgm ucode block */ + + if (rules->show_debug_info) { + /* Get the timestamp of the loaded microcode */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_TIMESTAMP1, + &yyyy); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_TIMESTAMP0, + &mmdd); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_TIMESTAMP2, + &hhmm); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_VERSION_KR, + &version_kr); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_VERSION_FC, + &version_fc); + /* Note that for now both KR and FC versions are set to 1 */ + if ((version_kr != 0) && (version_fc != 0)) { + CS_TRACE(("ERROR: uCode version is both KR + FC, KR(")); + CS_TRACE(("v.%04x),FC(v.%04x) built %04x/%04x/%04x\n", + version_kr, version_fc, yyyy, mmdd, hhmm)); + return CS_ERROR; + } + if (version_kr != 0) { + CS_PRINTF(("uCode on die %x: KR(v.%04x), built on", + die, version_kr)); + CS_PRINTF((" (yyyy/mmdd/hhmm) = %04x/%04x/%04x\n", + yyyy, mmdd, hhmm)); + } + if (version_fc != 0) { + CS_PRINTF(("uCode on die %x: FC(v.%04x), built on", + die, version_fc)); + CS_PRINTF((" (yyyy/mmdd/hhmm) = %04x/%04x/%04x\n", + yyyy, mmdd, hhmm)); + } + if (cs4224_max_num_dies == 2 && die_broadcast) { + /* Get the timestamp of the other loaded microcode */ + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_TIMESTAMP1, + &yyyy); + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_TIMESTAMP0, + &mmdd); + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_TIMESTAMP2, + &hhmm); + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_VERSION_KR, + &version_kr); + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_VERSION_FC, + &version_fc); + if (version_kr != 0) { + CS_PRINTF(("uCode on die %x: KR(v.%04x) built", + die, version_kr)); + CS_PRINTF((" (yyyy/mmdd/hhmm)=%04x/%04x/%04x\n", + yyyy, mmdd, hhmm)); + } + if (version_fc != 0) { + CS_PRINTF(("uCode on die %x: FC(v.%04x) built", + die, version_fc)); + CS_PRINTF((" (yyyy/mmdd/hhmm)=%04x/%04x/%04x\n", + yyyy, mmdd, hhmm)); + } + } + } + + /* power down all slices for bug #38832 */ + status |= cs4224_apply_workarounds_power_down(die); + if (die_broadcast) + status |= cs4224_apply_workarounds_power_down(other_die); + + return status; +} + +int cs4224_slice_enter_operational_state(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned int die = cs4224_get_die_from_slice(slice); + unsigned short data = 0; + + cs4224_sku_hw_id = CS4224_HW_UNDEF; + + /* Before we do anything, do some sanity checking of the rules */ + status |= cs4224_check_rules(slice, rules); + if (status != CS_OK) + return status; + + /* Before configuring the device, the die MUST have been reset and the + * EEPROM must already be loaded (if an EEPROM is available). Otherwise + * this method will exit immediately because it's unsafe to configure + * the device in this state. + */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + if (CS_IF_CLR(data, CS_BIT1)) { + CS_TRACE(("ERROR: cs4224_hard_reset hasn't been run on die\n")); + return CS_ERROR; + } + if (!cs4224_is_eeprom_finished(die)) { + CS_TRACE(("ERROR: EEPROM is still loading; aborting.\n")); + return CS_ERROR; + } + + /* Program the API version number */ + status |= cs4224_init_api_version(slice); + + /* Increment the slice configure count */ + status |= cs4224_update_scratch_regs(slice); + + /* Reset any static state stored by the slice */ + cs4224_reset_static_state_for_slice(slice); + + /* stall the microsequencer(s), always */ + if (cs4224_is_hw_simplex(slice)) { + status |= cs4224_mseq_stall(slice, CS4224_SPLX_MSEQ, CS_TRUE); + } else { + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_LINE_MSEQ, CS_TRUE); + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_HOST_MSEQ, CS_TRUE); + } + + /* Re-assert the squelch after stalling the microsequencer if it is not + * already squelched + */ + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH, 0x0001); + } + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH, 0x0001); + } + + if ((cs4224_is_hw_simplex(slice) && + (rules->rx_if.splx_edc_mode == CS_HSIO_EDC_MODE_DISABLED)) || + (cs4224_is_hw_duplex(slice) && + (rules->rx_if.dplx_line_edc_mode == CS_HSIO_EDC_MODE_DISABLED)) || + (cs4224_is_hw_duplex(slice) && + (rules->rx_if.dplx_host_edc_mode == CS_HSIO_EDC_MODE_DISABLED))) { + /* When using an eeprom image the mseq can set the squelch bit + * before we are able to stall it. This will force the bit high + * if we're in disabled mode and the mseq won't be unstalled. + */ + rules->unsquelch_driver = CS_TRUE; + } + + /* dump out debug info */ + if (rules->show_debug_info == CS_TRUE) + status |= cs4224_dump_debug_info(slice, rules); + + /* Apply post-reset configuration and program the microcode */ + status |= cs4224_manage_ucode_download(slice, rules); + if (status != CS_OK) { + /* ucode download has a lot of potential to go wrong, exit */ + CS_TRACE(("ERROR: Ucode download on slice %x failed, exiting\n", + slice)); + return status; + } + + /* Apply a soft reset to put the slice in a known state. + * This only really helps dynamic reconfig. + */ + if (rules->application != CS4224_TARGET_APPLICATION_FCAN) + status |= cs4224_slice_soft_reset(slice); + + status |= cs4224_config_target_application(slice, rules); + + status |= cs4224_update_clkdiv_ctrl(slice, rules); + + status |= cs4224_init_driver_trace_loss(slice, rules); + + status |= cs4224_init_edc_mode_set(slice, rules); + + status |= cs4224_update_cdr_fracn(slice, rules); + + if (cs4224_is_hw_simplex(slice)) + status |= cs4224_mseq_enable_power_savings( + slice, CS4224_SPLX_MSEQ, rules->enable_power_savings); + else { + if (rules->application != CS4224_TARGET_APPLICATION_FCAN) { + /* the FC-AN ucode configures the line side DFE mode, + * do not muck around with power savings here... + */ + status |= cs4224_mseq_enable_power_savings( + slice, CS4224_DPLX_LINE_MSEQ, + rules->enable_power_savings); + } + status |= cs4224_mseq_enable_power_savings( + slice, CS4224_DPLX_HOST_MSEQ, + rules->enable_power_savings); + } + + status |= cs4224_init_alt_coarse_tuning(slice, rules); + status |= cs4224_disable_tx_driver_if_req(slice, rules); + status |= cs4224_init_ac_decoupling_caps(slice, rules); + status |= cs4224_init_mseq_dyn_reconfig(slice, rules); + + cs4224_lock(slice); + + /* coarse tune VCOs because ref clock is not at 106.25Mhz */ + + /* Enable then trigger VCO coarse tuning */ + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_get_channel(slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + &data); + status |= cs4224_reg_set_channel(slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x01e7); + CS_MDELAY(1); + + /* init_vco has built-in delays after coarse tuning */ + status |= cs4224_init_vco(slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_CONTROL); + + if ((data & 0x1c0) != 0x1c0) { + /* demux enabled, needs staggered power up */ + status |= cs4224_reg_set_channel(slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + (data | 0x1f)); + } + status |= cs4224_reg_set_channel(slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + data); + } + + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_get_channel(slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + &data); + status |= cs4224_reg_set_channel(slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x01e7); + CS_MDELAY(1); + + /* init_vco has built-in delays after coarse tuning */ + status |= cs4224_init_vco(slice, + CS4224_PP_HOST_SDS_COMMON_RXVCO0_CONTROL); + + if ((data & 0x1c0) != 0x1c0) { + /* demux enabled, needs staggered power up */ + status |= cs4224_reg_set_channel(slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + (data | 0x1f)); + } + + status |= cs4224_reg_set_channel(slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + data); + } + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_mseq_squelch_ctrl( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, + rules->tx_auto_squelch); + } + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_mseq_squelch_ctrl( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, + rules->tx_auto_squelch); + } + + /* Unsquelching before the microcode is unstalled to prevent ordering + * issues. See bug #41747 for details. + */ + if (rules->unsquelch_driver) { + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + /* remove any pending squelch requests */ + status |= cs4224_clear_mailbox(slice, + CS4224_DPLX_LINE_MSEQ); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH, + 0x0000); + } + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + /* remove any pending squelch requests */ + status |= cs4224_clear_mailbox(slice, + CS4224_DPLX_HOST_MSEQ); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH, + 0x0000); + } + } + + /* do not start microsequencer if protocol running on the line side */ + if ((rules->application != CS4224_TARGET_APPLICATION_10G_KR) && + (rules->application != CS4224_TARGET_APPLICATION_40G_KR) && + (rules->application != CS4224_TARGET_APPLICATION_KRAN) && + (rules->application != CS4224_TARGET_APPLICATION_FCAN)) { + /* un-stall the microsequencer(s), if required */ + if (cs4224_is_hw_simplex(slice)) { + if (rules->rx_if.splx_edc_mode != + CS_HSIO_EDC_MODE_DISABLED) { + status |= cs4224_mseq_stall( + slice, CS4224_SPLX_MSEQ, CS_FALSE); + } + } else { /* duplex */ + if (rules->rx_if.dplx_line_edc_mode != + CS_HSIO_EDC_MODE_DISABLED) + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_LINE_MSEQ, CS_FALSE); + if (rules->rx_if.dplx_host_edc_mode != + CS_HSIO_EDC_MODE_DISABLED) + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_HOST_MSEQ, CS_FALSE); + } + } + + cs4224_unlock(slice); + + return status; +} + +unsigned int cs4224_get_die_from_slice(unsigned int slice) +{ + unsigned int die = 0; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + /* Save the upper bits to pass thru to the die parameter */ + unsigned int upper_bits = slice & 0xffffff00; + + switch (hw_id) { + case CS4224_HW_CS4223: /* 4 port duplex */ + case CS4224_HW_CS4227: /* 2 port duplex */ + die = 0; + break; + + case CS4224_HW_CS4343: /* 8 port duplex */ + case CS4224_HW_CS4341: + /* Only the lower 8 bits belong to the API. They represent + * the duplex channel (0-7) of the device. + */ + if ((slice & 0xFF) > 3) + die = 0; + else + die = 1; + break; + + case CS4224_HW_CS4224: /* 16 port simplex */ + case CS4224_HW_CS4210: + /* Only the lower 8 bits belong to the API. They represent + * the simplex channel (0-15) of the device. + */ + if ((slice & 0xFF) > 7) + die = 0; + else + die = 1; + break; + + case CS4224_HW_CS4221: /* 10 port simplex */ + /* Only the lower 8 bits belong to the API. They represent + * the duplex channel (0-9) of the device. + */ + if ((slice & 0xFF) > 4) + die = 0; + else + die = 1; + break; + + default: + CS_TRACE(("ERROR: HW ID not valid, hw_id = %x\n", hw_id)); + die = 0; + break; + } + + return die | upper_bits; +} + +int cs4224_reg_get_channel(unsigned int slice, unsigned int addr, + unsigned short *data) +{ + unsigned int die = 0; + int status = CS_OK; + + /* If the address has not already been adjusted + * then do the port pair adjustment here + */ + if ((addr >= 0x1000) && (addr < 0x5000)) { + /* Mask out the upper bits if they have already been adjusted */ + addr = (addr | 0x3000) & 0x1fff; + + /* guard against reading from bad registers */ + if (!cs4224_diags_register_can_read((unsigned short)addr)) { + *data = 0xbeef; + return CS_OK; + } + + /* Now adjust them to access the proper port pair */ + addr = cs4224_adj_pp(slice, addr); + + /* CS_PRINTF(("after slice = %d, addr = %x\n", slice, addr));*/ + } + /* Handle the MSEQ_PS space */ + else if ((addr >= 0x300) && (addr < 0x500)) { + /* Mask out any upper bits if they have already been adjusted */ + addr = (addr | 0x300) & 0x3ff; + addr = cs4224_adj_mseq(slice, addr); + } + + /* get the die associated with this slice */ + die = cs4224_get_die_from_slice(slice); + + /* Set the die but make sure to pass the upper 24 bits of the + * slice parameter through to the lower level API. These are + * used by the customer to address multiple devices + */ + status |= cs4224_reg_get(die | (slice >> 8 << 8), addr, data); + + return status; +} + +unsigned short cs4224_reg_read(unsigned int slice, unsigned int addr) +{ + unsigned short data; + int status = CS_OK; + + status |= cs4224_reg_get_channel(slice, addr, &data); + if (status != CS_OK) { + CS_TRACE( + ("ERROR: reg get failed; status %x, returning 0xDEAD\n", + status)); + data = 0xDEAD; + } + + return data; +} + +int cs4224_reg_set_channel(unsigned int slice, unsigned int addr, + unsigned short data) +{ + unsigned int die = 0; + + /* If the PP address has not already been adjusted + * then do the port pair adjustment here + */ + if ((addr >= 0x1000) && (addr < 0x5000)) { + /* Mask out the upper bits if they have already been adjusted */ + addr = (addr | 0x3000) & 0x1fff; + + /* Now adjust them to access the proper port pair */ + addr = cs4224_adj_pp(slice, addr); + } + /* Handle the MSEQ_PS space */ + else if ((addr >= 0x300) && (addr < 0x500)) { + /* Mask out any upper bits if they have already been adjusted */ + addr = (addr | 0x300) & 0x3ff; + addr = cs4224_adj_mseq(slice, addr); + } + + /* get the die associated with this slice */ + die = cs4224_get_die_from_slice(slice); + + /* Set the die but make sure to pass the upper 24 bits of the + * slice parameter through to the lower level API. These are + * used by the customer to address multiple devices + */ + return cs4224_reg_set(die | (slice >> 8 << 8), addr, data); +} + +int cs4224_reg_set_chk_channel(unsigned int slice, unsigned int addr, + unsigned short data) +{ + int status = CS_OK; + unsigned short get_data = 0; + + status |= cs4224_reg_set_channel(slice, addr, data); + status |= cs4224_reg_get_channel(slice, addr, &get_data); + if (get_data != data) { + CS_TRACE( + ("ERROR: Data was written to register\n")); + CS_PRINTF( + ("reg addr: %4x data written: %4x data read: %4x\n", + addr, data, get_data)); + status |= CS_ERROR; + } + return status; +} + +const char *cs4224_translate_edc_mode(enum e_cs4224_edc_mode edc_mode) +{ + switch (edc_mode) { + case CS_HSIO_EDC_MODE_DISABLED: { + return "CS_HSIO_EDC_MODE_DISABLED"; + } + case CS_HSIO_EDC_MODE_CX1: { + return "CS_HSIO_EDC_MODE_CX1"; + } + case CS_HSIO_EDC_MODE_SR: { + return "CS_HSIO_EDC_MODE_SR"; + } + case CS_HSIO_EDC_MODE_ZR: { + return "CS_HSIO_EDC_MODE_ZR"; + } + case CS_HSIO_EDC_MODE_DWDM: { + return "CS_HSIO_EDC_MODE_DWDM"; + } + case CS_HSIO_EDC_MODE_10G_BP: { + return "CS_HSIO_EDC_MODE_10G_BP"; + } + case CS_HSIO_EDC_MODE_15G_BP: { + return "CS_HSIO_EDC_MODE_15G_BP"; + } + case CS_HSIO_EDC_MODE_15G_BP_27dB: { + return "CS_HSIO_EDC_MODE_15G_BP_27dB"; + } + case CS_HSIO_EDC_MODE_5G_BP: { + return "CS_HSIO_EDC_MODE_5G_BP"; + } + case CS_HSIO_EDC_MODE_7p5G_BP: { + return "CS_HSIO_EDC_MODE_7p5G_BP"; + } + case CS_HSIO_EDC_MODE_8p5G_BP: { + return "CS_HSIO_EDC_MODE_8p5G_BP"; + } + case CS_HSIO_EDC_MODE_FCAN: { + return "CS_HSIO_EDC_MODE_FCAN"; + } + case CS_HSIO_EDC_MODE_SMLRM: { + return "CS_HSIO_EDC_MODE_SMLRM"; + } + } + + return "UNKNOWN EDC MODE"; +} + +const char *cs4224_translate_app_mode(enum e_cs4224_target_application app_mode) +{ + switch (app_mode) { + case CS4224_TARGET_APPLICATION_1G: { + return "CS4224_TARGET_APPLICATION_1G"; + } + case CS4224_TARGET_APPLICATION_5G: { + return "CS4224_TARGET_APPLICATION_5G"; + } + case CS4224_TARGET_APPLICATION_7p5G: { + return "CS4224_TARGET_APPLICATION_7p5G"; + } + case CS4224_TARGET_APPLICATION_8G: { + return "CS4224_TARGET_APPLICATION_8G"; + } + case CS4224_TARGET_APPLICATION_8p5G: { + return "CS4224_TARGET_APPLICATION_8p5G"; + } + case CS4224_TARGET_APPLICATION_10G: { + return "CS4224_TARGET_APPLICATION_10G"; + } + case CS4224_TARGET_APPLICATION_15G: { + return "CS4224_TARGET_APPLICATION_15G"; + } + case CS4224_TARGET_APPLICATION_10G_KR: { + return "CS4224_TARGET_APPLICATION_10G_KR"; + } + case CS4224_TARGET_APPLICATION_40G_KR: { + return "CS4224_TARGET_APPLICATION_40G_KR"; + } + case CS4224_TARGET_APPLICATION_KRAN: { + return "CS4224_TARGET_APPLICATION_KRAN"; + } + case CS4224_TARGET_APPLICATION_FCAN: { + return "CS4224_TARGET_APPLICATION_FCAN"; + } + case CS4224_TARGET_APPLICATION_16G_FC: { + return "CS4224_TARGET_APPLICATION_16G_FC"; + } + case CS4224_TARGET_APPLICATION_10G_FC: { + return "CS4224_TARGET_APPLICATION_10G_FC"; + } + case CS4224_TARGET_APPLICATION_8G_FC: { + return "CS4224_TARGET_APPLICATION_8G_FC"; + } + case CS4224_TARGET_APPLICATION_4G_FC: { + return "CS4224_TARGET_APPLICATION_4G_FC"; + } + case CS4224_TARGET_APPLICATION_2G_FC: { + return "CS4224_TARGET_APPLICATION_2G_FC"; + } + case CS4224_TARGET_APPLICATION_1G_FC: { + return "CS4224_TARGET_APPLICATION_1G_FC"; + } + case CS4224_TARGET_APPLICATION_OC12: { + return "CS4224_TARGET_APPLICATION_OC12"; + } + } + + return "UNKNOWN APP MODE"; +} + +const char *cs4224_switch_translate_state(enum e_cs4224_switch_action_t state) +{ + switch (state) { + case CS4224_SWITCH_DISABLE: + return "CS4224_SWITCH_DISABLE"; + case CS4224_SWITCH_DUPLEX_BROADCAST_1_to_1: + return "CS4224_SWITCH_DUPLEX_BROADCAST_1_to_1"; + case CS4224_SWITCH_DUPLEX_BROADCAST_0_to_0: + return "CS4224_SWITCH_DUPLEX_BROADCAST_0_to_0"; + case CS4224_SWITCH_DUPLEX_BROADCAST_0_to_1: + return "CS4224_SWITCH_DUPLEX_BROADCAST_0_to_1"; + case CS4224_SWITCH_DUPLEX_BROADCAST_1_to_0: + return "CS4224_SWITCH_DUPLEX_BROADCAST_1_to_0"; + case CS4224_SWITCH_DUPLEX_SWITCH_2x2: + return "CS4224_SWITCH_DUPLEX_SWITCH_2x2"; + case CS4224_SWITCH_SIMPLEX_SWITCH_2x2: + return "CS4224_SWITCH_SIMPLEX_SWITCH_2x2"; + case CS4224_SWITCH_SIMPLEX_BROADCAST: + return "CS4224_SWITCH_SIMPLEX_BROADCAST"; + + default: + break; + } + + return "???"; +} + +const char *cs4224_translate_cfg_side(enum e_cs4224_cfg_sides_t side) +{ + switch (side) { + case CS4224_CFG_HOST_SIDE: + return "host"; + case CS4224_CFG_LINE_SIDE: + return "line"; + case CS4224_CFG_SIMPLEX: + return "splx"; + default: + break; + } + return "????"; +} + +#if !defined(CS_SKIP_UCODE_DOWNLOAD) + +int cs4224_ucode_data_prgm_image(unsigned int slice, unsigned short microcode[], + unsigned int len_buffer) +{ + unsigned int i; + int status = CS_OK; + unsigned short data0, data1; + unsigned int die; + + /* get the die associated to this slice */ + die = cs4224_get_die_from_slice(slice); + + /* toggle the checksum calculator, note that the file data will + * assert the checksum bit to start calculating the checksum + */ + cs4224_lock(slice); + cs4224_reg_set(die, CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL, 0x01); + cs4224_reg_set(die, CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL, 0x00); + cs4224_unlock(slice); + + for (i = 0; i < len_buffer; i += 2) { + unsigned short addr = microcode[i]; + unsigned short data = microcode[i + 1]; + unsigned short access_status = 0; + short max_iterations = 100; + + /* Program data here */ + cs4224_lock(slice); + + status |= cs4224_reg_set(die, addr, data); + + /* If this is a write to the EEPROM_MICRO_ACCESS_CONTROL + * then wait for the previous access to finish. + */ + if (addr == CS4224_EEPROM_MICRO_ACCESS_CONTROL) { + /* Wait for EEPROM_MICRO_ACCESS_STATUS.MicroAccessDone + * bit to be set. + */ + while (CS_IF_CLR(access_status, CS_BIT0) && + (max_iterations > 0)) { + cs4224_reg_get( + die, CS4224_EEPROM_MICRO_ACCESS_STATUS, + &access_status); + max_iterations -= 1; + } + + if (max_iterations <= 0) { + CS_TRACE(("ERROR: Timed out on die %x\n", die)); + return CS_ERROR; + } + } + + cs4224_unlock(slice); + } + + status |= cs4224_reg_get(die, CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS, + &data0); + if (data0 == 0x1) { + status |= cs4224_reg_get(die, CS4224_GLOBAL_DWNLD_CHECKSUM_HW, + &data0); + status |= cs4224_reg_get(die, CS4224_GLOBAL_DWNLD_CHECKSUM_SW, + &data1); + CS_TRACE( + ("ERROR: Comms issue! checksum: img=0x%04x,hw=0x%04x\n", + data1, data0)); + status |= CS_ERROR; + } + + return status; +} + +unsigned int cs4224_calc_crc16(unsigned int input_data, unsigned int crc_init) +{ + unsigned int i, j, crc; + unsigned int tmp, msb, data = 0; + + crc = crc_init & 0x0000ffff; + + for (i = 0; i < 4; i++) { + if (i == 0) + data = (input_data & 0xff000000) >> 24; + if (i == 1) + data = (input_data & 0x00ff0000) >> 16; + if (i == 2) + data = (input_data & 0x0000ff00) >> 8; + if (i == 3) + data = (input_data & 0xff0000ff) >> 0; + + tmp = 0x000080; + + for (j = 0; j < 8; j++) { + msb = crc & 0x8000; + crc <<= 1; + crc &= 0x0000ffff; + if (data & tmp) + msb ^= 0x00008000; + if (msb) + crc ^= 0x1021; + tmp >>= 1; + } + } + return crc; +} + +enum e_cs4224_ucode_crc16_t { + CS4224_UCODE_PRE_CRC16_CALC = 1, /* Pre CRC-16 calculation state */ + CS4224_UCODE_ACTIVE_CRC16_CALC = 2, /* CRC-16 calculation state */ + CS4224_UCODE_POST_CRC16_CALC = 3, /* Post CRC-16 calculation state */ +}; + +int cs4224_ucode_data_prgm_image_broadcast(unsigned int slice, + unsigned short microcode[], + unsigned int len_buffer) +{ + unsigned int i; + int status = CS_OK; + int tmp_status = CS_OK; + unsigned short checksum, data; + unsigned int crc_sw = 0xffff; + unsigned int crc_hw = 0xffff; + unsigned int input_data_hw, input_data_sw; + enum e_cs4224_ucode_crc16_t crc_sm = CS4224_UCODE_PRE_CRC16_CALC; + + /* upper bits of slice used to pick chip being used */ + unsigned int upper_bits = slice & 0xffffff00; + + if (!microcode || len_buffer == 0) + return CS_ERROR; + + /* Ensure the MDIO timeout is increased on both dies, Bugzilla 35875 */ + status |= cs4224_reg_set(0 | upper_bits, CS4224_GLOBAL_MDIO_CONFIG, + CS4224_GLOBAL_MDIO_CONFIG_pref); + status |= cs4224_reg_set(1 | upper_bits, CS4224_GLOBAL_MDIO_CONFIG, + CS4224_GLOBAL_MDIO_CONFIG_pref); + + /* config to broadcast to both dies */ + data = 0x0100; + + /* force die 1 to listen to die 0's address */ + /* ignore the status returned by the reg set since an I2C transaction + * will fail to get the checksum + */ + cs4224_reg_set(1 | upper_bits, CS4224_GLOBAL_BROADCAST, data); + + if (status != CS_OK) + return status; + + for (i = 0; i < len_buffer; i += 2) { + unsigned short addr = microcode[i]; + unsigned short data = microcode[i + 1]; + + if (addr == CS4224_EEPROM_MICRO_ACCESS_CONTROL) { + CS_TRACE(("ERROR: Cannot program the EEPROM bcast!\n")); + + /* disable broadcasting to both dies */ + cs4224_reg_set(0 | upper_bits, CS4224_GLOBAL_BROADCAST, + 0x0000); + + return CS_ERROR; + } + + if (crc_sm == CS4224_UCODE_ACTIVE_CRC16_CALC) { + /* calculate our own crc that will mirror the one in + * the image, without the below BROADCAST trap + */ + input_data_sw = (addr << 16) + data; + crc_sw = cs4224_calc_crc16(input_data_sw, crc_sw); + } + + if (addr == CS4224_GLOBAL_BROADCAST) { + /* intercept to ensure the broadcast bit remains set */ + data |= 0x0100; + } + + if (crc_sm == CS4224_UCODE_ACTIVE_CRC16_CALC) { + /* calculate our own crc that that will mirror the + * HW calculated one, + * with the above BROADCAST trap + */ + input_data_hw = (addr << 16) + data; + crc_hw = cs4224_calc_crc16(input_data_hw, crc_hw); + } + + cs4224_lock(slice); + + /* Program hw here */ + tmp_status = cs4224_reg_set(0 | upper_bits, addr, data); + + cs4224_unlock(slice); + + if (addr != CS4224_GLOBAL_BROADCAST) { + /* ignore the status of writes to BROADCAST */ + status |= tmp_status; + } + + if (status != CS_OK) { + /* some kind of legitimate write issue */ + CS_TRACE( + ("ERROR: cs4224_reg_set(0x%x, 0x%x, 0x%x)\n", + upper_bits, + addr, + data)); + + /* disable broadcasting to both dies */ + cs4224_reg_set(0 | upper_bits, CS4224_GLOBAL_BROADCAST, + 0x0000); + + return CS_ERROR; + } + + /* update our checksum calculator state machine */ + if (addr == CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL) { + if (data == 0x0001) { + /* HW CRC-16 calculator enabled */ + crc_sm = CS4224_UCODE_ACTIVE_CRC16_CALC; + } else { + /* HW CRC-16 calculator disabled */ + crc_sm = CS4224_UCODE_POST_CRC16_CALC; + } + } + } + + /* disable broadcasting to both dies */ + status |= cs4224_reg_set(0 | upper_bits, CS4224_GLOBAL_BROADCAST, + 0x0000); + + /* get the image checksum */ + status |= cs4224_reg_get(0 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_SW, + &checksum); + + /* compare our mirror checksum with the image checksum, this + * checks that OUR program memory or wherever we got the image from + * isn't corrupted + */ + if (crc_sw != checksum) { + CS_TRACE(("ERROR: (image corrupt?),calc=0x%04x, image=0x%04x\n", + crc_sw, + checksum)); + status |= CS_ERROR; + } + + /* write our calculated hardware checksum to CHECKSUM_SW reg so the + * CHECKSUM_STATUS clears + */ + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_SW, + crc_hw); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_SW, + crc_hw); + + /* check that the chip hw checksum and our calculated + * crc_hw checksum match + */ + status |= cs4224_reg_get(0 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS, + &data); + if (data == 0x1) { + status |= cs4224_reg_get(0 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_HW, + &checksum); + CS_TRACE(("ERROR: Comms issue checksum calc=0x%04x,hw=0x%04x\n", + crc_hw, + checksum)); + status |= CS_ERROR; + } + + status |= cs4224_reg_get(1 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS, + &data); + if (data == 0x1) { + status |= cs4224_reg_get(1 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_HW, + &checksum); + CS_TRACE(("ERROR: checksum match, calc=0x%04x, hw=0x%04x\n", + crc_hw, + checksum)); + status |= CS_ERROR; + } + + if (status != CS_OK) { + /* Clear the timestamps */ + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP0, + 0x0); + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP1, + 0x0); + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP2, + 0x0); + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_VERSION_KR, + 0x0); + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_VERSION_FC, + 0x0); + + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP0, + 0x0); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP1, + 0x0); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP2, + 0x0); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_VERSION_KR, + 0x0); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_VERSION_FC, + 0x0); + } + + return status; +} + +#endif /* !CS_SKIP_UCODE_DOWNLOAD */ diff --git a/include/cortina_api.h b/include/cortina_api.h new file mode 100644 index 0000000000..ae90ae324d --- /dev/null +++ b/include/cortina_api.h @@ -0,0 +1,2822 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Cortina PHY drivers framework + * + * Copyright 2018-2021 NXP + * Copyright (C) 2006-2017 Inphi Corporation, Inc. All rights reserved. + */ + +#ifndef __CORTINA_API_H_ +#define __CORTINA_API_H_ + +#include +#include +#include +#include +#include +#include +#include + +/* endiannes */ +#define CS_LITTLE_ENDIAN + +/* Things that can be tweaked */ +#define CS_PRINTF(x) debug x +#define CS_FPRINTF(x) fprintf x +#define CS_FLUSH() fflush(stdout) +#define CS_SNPRINTF(x) snprintf x +#define CS_TRACE(x) debug x +#define CS_UDELAY(x) udelay((x)) +#define CS_MDELAY(x) udelay((x)*1000) + +/* Make sure endianess is defined */ +#ifdef CS_BIG_ENDIAN +# ifdef CS_LITTLE_ENDIAN +# error "CS_BIG_ENDIAN and CS_LITTLE_ENDIAN are both defined." +# endif +#else +# ifndef CS_LITTLE_ENDIAN +# error "Either CS_BIG_ENDIAN or CS_LITTLE_ENDIAN must be defined." +# endif +#endif + +/* Cortina/Inphi reference software version */ +#define CS_API_VERSION "3.10.0" +#define CS_API_BUILD_DATE "Apr 21, 2017 at 16:09:26" + +#define CS_API_VERSION_MAJOR 3 +#define CS_API_VERSION_MINOR 10 +#define CS_API_VERSION_UPDATE 0 + +#define CS_OK 0 +#define CS_ERROR -1 + +#define CS_TRUE 1 +#define CS_FALSE 0 + +#ifndef NULL +#define NULL 0 +#endif + +/* Chip family defines */ +#define CS4224_GLOBAL_CHIP_ID_LSB 0x0 +#define CS4224_GLOBAL_CHIP_ID_LSB_dft 0x3E5 +#define CS4224_GLOBAL_CHIP_ID_MSB 0x1 +#define CS4224_GLOBAL_CHIP_ID_MSB_dft 0x7003 +#define CS4224_GLOBAL_SCRATCH 0x2 +#define CS4224_GLOBAL_SCRATCH_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_SR 0x3 +#define CS4224_GLOBAL_UCODE_VERSION_SR_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_CX1 0x4 +#define CS4224_GLOBAL_UCODE_VERSION_CX1_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_KR 0x5 +#define CS4224_GLOBAL_UCODE_VERSION_KR_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_ZR 0x6 +#define CS4224_GLOBAL_UCODE_VERSION_ZR_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_FC 0x7 +#define CS4224_GLOBAL_UCODE_VERSION_FC_dft 0x0 +#define CS4224_GLOBAL_UCODE_TIMESTAMP0 0x8 +#define CS4224_GLOBAL_UCODE_TIMESTAMP0_dft 0x0 +#define CS4224_GLOBAL_UCODE_TIMESTAMP1 0x9 +#define CS4224_GLOBAL_UCODE_TIMESTAMP1_dft 0x0 +#define CS4224_GLOBAL_UCODE_TIMESTAMP2 0xA +#define CS4224_GLOBAL_UCODE_TIMESTAMP2_dft 0x0 +#define CS4224_GLOBAL_MPIF_SOFT_RESET 0xD +#define CS4224_GLOBAL_MPIF_SOFT_RESET_dft 0x0 +#define CS4224_GLOBAL_MDIO_CONFIG 0xF +#define CS4224_GLOBAL_MDIO_CONFIG_dft 0x50 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL 0x11 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL_dft 0x0 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS 0x12 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS_dft 0x0 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_HW 0x13 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_HW_dft 0xFFFF +#define CS4224_GLOBAL_DWNLD_CHECKSUM_SW 0x14 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_SW_dft 0x0 +#define CS4224_GLOBAL_PIN_STATUS 0x16 +#define CS4224_GLOBAL_PIN_STATUS_dft 0x0 +#define CS4224_GLOBAL_BROADCAST 0x17 +#define CS4224_GLOBAL_BROADCAST_dft 0x0 +#define CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT1 0x18 +#define CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT1_dft 0x0 +#define CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT0 0x19 +#define CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT0_dft 0x3CF0 +#define CS4224_GLOBAL_SCRATCH0 0x1D +#define CS4224_GLOBAL_SCRATCH0_dft 0x0 +#define CS4224_GLOBAL_SCRATCH6 0x23 +#define CS4224_GLOBAL_SCRATCH6_dft 0x0 +#define CS4224_GLOBAL_SCRATCH7 0x24 +#define CS4224_GLOBAL_SCRATCH7_dft 0x0 +#define CS4224_GLOBAL_GLOBAL_INTERRUPT 0x26 +#define CS4224_GLOBAL_GLOBAL_INTERRUPT_dft 0x0 +#define CS4224_GLOBAL_GLOBAL_INTE 0x27 +#define CS4224_GLOBAL_GLOBAL_INTE_dft 0x0 +#define CS4224_GLOBAL_DATAPATH_INTERRUPT 0x28 +#define CS4224_GLOBAL_DATAPATH_INTERRUPT_dft 0x0 +#define CS4224_GLOBAL_DATAPATH_INTE 0x29 +#define CS4224_GLOBAL_DATAPATH_INTE_dft 0x0 +#define CS4224_GPIO_INTERR 0x100 +#define CS4224_GPIO_INTERR_dft 0x0 +#define CS4224_GPIO_GPIO1 0x106 +#define CS4224_GPIO_GPIO1_dft 0x0 +#define CS4224_GPIO_GPIO2 0x10C +#define CS4224_GPIO_GPIO2_dft 0x0 +#define CS4224_GPIO_GPIO3 0x112 +#define CS4224_GPIO_GPIO3_dft 0x0 +#define CS4224_GPIO_GPIO4 0x118 +#define CS4224_GPIO_GPIO4_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT0 0x11E +#define CS4224_GPIO_GPIO_INPUT0_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT_INT 0x124 +#define CS4224_GPIO_GPIO_INPUT_INT_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT_INTE 0x125 +#define CS4224_GPIO_GPIO_INPUT_INTE_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT_INTS 0x126 +#define CS4224_GPIO_GPIO_INPUT_INTS_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT_INTZ 0x127 +#define CS4224_GPIO_GPIO_INPUT_INTZ_dft 0x0 +#define CS4224_EFUSE_GENERAL_STATUS 0x181 +#define CS4224_EFUSE_GENERAL_STATUS_dft 0x0 +#define CS4224_EFUSE_PDF_SKU 0x19F +#define CS4224_EFUSE_PDF_SKU_dft 0x0 +#define CS4224_EFUSE_PDF_MON_CAL_DATA 0x1A4 +#define CS4224_EFUSE_PDF_MON_CAL_DATA_dft 0x0 +#define CS4224_EFUSE_PDF_MON_GAIN_DATA 0x1A5 +#define CS4224_EFUSE_PDF_MON_GAIN_DATA_dft 0x0 +#define CS4224_EFUSE_PDF_MON_LUT15 0x1A6 +#define CS4224_EFUSE_PDF_MON_LUT15_dft 0x0 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA2 0x1B7 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA2_dft 0x0 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA1 0x1B8 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA1_dft 0x0 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA0 0x1B9 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA0_dft 0x0 +#define CS4224_MONITOR_CONTROL0 0x200 +#define CS4224_MONITOR_CONTROL0_dft 0x630C +#define CS4224_MONITOR_CONFIG_MASK 0x204 +#define CS4224_MONITOR_CONFIG_MASK_dft 0x0 +#define CS4224_MONITOR_LUT_SELECT 0x20B +#define CS4224_MONITOR_LUT_SELECT_dft 0x0 +#define CS4224_MONITOR_LUT_LOCAL_SELECT 0x20C +#define CS4224_MONITOR_LUT_LOCAL_SELECT_dft 0x0 +#define CS4224_MONITOR_LUT_APPLY 0x20D +#define CS4224_MONITOR_LUT_APPLY_dft 0x0 +#define CS4224_MONITOR_CAL_CONST_OVERRIDE_ENA 0x20E +#define CS4224_MONITOR_CAL_CONST_OVERRIDE_ENA_dft 0x0 +#define CS4224_MONITOR_CAL_OVERRIDE 0x20F +#define CS4224_MONITOR_CAL_OVERRIDE_dft 0x0 +#define CS4224_MONITOR_CAL_CONST_APPLY 0x210 +#define CS4224_MONITOR_CAL_CONST_APPLY_dft 0x0 +#define CS4224_MONITOR_STATUS_FINAL0 0x25A +#define CS4224_MONITOR_STATUS_FINAL0_dft 0x0 +#define CS4224_MONITOR_STATUS_FINAL2 0x25C +#define CS4224_MONITOR_STATUS_FINAL2_dft 0x0 +#define CS4224_MONITOR_STATUS_FINAL6 0x260 +#define CS4224_MONITOR_STATUS_FINAL6_dft 0x0 +#define CS4224_MONITOR_LUT_RANGE0 0x27B +#define CS4224_MONITOR_LUT_RANGE0_dft 0x0 +#define CS4224_MONITOR_LUT_VALUE0 0x28B +#define CS4224_MONITOR_LUT_VALUE0_dft 0x0 +#define CS4224_CLKMON_GBL_CLKSEL 0x2E0 +#define CS4224_CLKMON_GBL_CLKSEL_dft 0x7F +#define CS4224_CLKMON_GBL_CTRL 0x2E1 +#define CS4224_CLKMON_GBL_CTRL_dft 0x110 +#define CS4224_CLKMON_GBL_DURATION 0x2E2 +#define CS4224_CLKMON_GBL_DURATION_dft 0x0 +#define CS4224_CLKMON_GBL_MINTHRESH1 0x2E6 +#define CS4224_CLKMON_GBL_MINTHRESH1_dft 0x0 +#define CS4224_CLKMON_GBL_MINTHRESH0 0x2E7 +#define CS4224_CLKMON_GBL_MINTHRESH0_dft 0x0 +#define CS4224_CLKMON_GBL_MAXTHRESH1 0x2E8 +#define CS4224_CLKMON_GBL_MAXTHRESH1_dft 0x0 +#define CS4224_CLKMON_GBL_MAXTHRESH0 0x2E9 +#define CS4224_CLKMON_GBL_MAXTHRESH0_dft 0x0 +#define CS4224_MSEQ_PS_RAM_CONTROL 0x301 +#define CS4224_MSEQ_PS_RAM_CONTROL_dft 0x0 +#define CS4224_MSEQ_PS_RAM_DATA1 0x302 +#define CS4224_MSEQ_PS_RAM_DATA1_dft 0x0 +#define CS4224_MSEQ_PS_RAM_DATA0 0x303 +#define CS4224_MSEQ_PS_RAM_DATA0_dft 0x0 +#define CS4224_MSEQ_PS_INT 0x306 +#define CS4224_MSEQ_PS_INT_dft 0x0 +#define CS4224_MSEQ_PS_INTE 0x307 +#define CS4224_MSEQ_PS_INTE_dft 0x0 +#define CS4224_MSEQ_PS_INTO 0x308 +#define CS4224_MSEQ_PS_INTO_dft 0x0 +#define CS4224_MSEQ_PS_INTZ 0x309 +#define CS4224_MSEQ_PS_INTZ_dft 0x0 +#define CS4224_MSEQ_PS_MBIST_CTRL 0x30A +#define CS4224_MSEQ_PS_MBIST_CTRL_dft 0x0 +#define CS4224_MSEQ_PS_MBIST_STATUS 0x30B +#define CS4224_MSEQ_PS_MBIST_STATUS_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_SOFT_RESET 0x1000 +#define CS4224_PP_LINE_LINEMISC_SOFT_RESET_dft 0x2 +#define CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG 0x1001 +#define CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG_dft 0x7 +#define CS4224_PP_LINE_LINEMISC_GIGEPCS_SOFT_RESET 0x1002 +#define CS4224_PP_LINE_LINEMISC_GIGEPCS_SOFT_RESET_dft 0x3 +#define CS4224_PP_LINE_LINEMISC_FUNCEN 0x1003 +#define CS4224_PP_LINE_LINEMISC_FUNCEN_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_CLKEN 0x1004 +#define CS4224_PP_LINE_LINEMISC_CLKEN_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL 0x1007 +#define CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL_dft 0x4 +#define CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL 0x100B +#define CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL_dft 0xF180 +#define CS4224_PP_LINE_LINEMISC_KR_AN_PORT_ADDR 0x100C +#define CS4224_PP_LINE_LINEMISC_KR_AN_PORT_ADDR_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_AN_MODE_SEL 0x100D +#define CS4224_PP_LINE_LINEMISC_AN_MODE_SEL_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_OVERRIDE_EN 0x1010 +#define CS4224_PP_LINE_LINEMISC_OVERRIDE_EN_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_INTERRUPT 0x1011 +#define CS4224_PP_LINE_LINEMISC_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_INTENABLE 0x1012 +#define CS4224_PP_LINE_LINEMISC_INTENABLE_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RX0_Config 0x1020 +#define CS4224_PP_LINE_SDS_COMMON_RX0_Config_dft 0x18 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG 0x1021 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL 0x1023 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL_dft 0x3005 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKOUT_CTRL 0x1024 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKOUT_CTRL_dft 0x2FF +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA 0x1027 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA_dft 0x77 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE 0x1029 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE 0x102A +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE_dft 0x44 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_MISC 0x102D +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_MISC_dft 0x300 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE 0x102F +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE_dft 0xE0F0 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON 0x1030 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_VCOMAX 0x1031 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_VCOMAX_dft 0xFFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_CONTROL 0x1033 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_CONTROL_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI 0x1035 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_STATUS 0x1037 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_STATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL3 0x1039 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL3_dft 0xFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL2 0x103A +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL2_dft 0xFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL1 0x103B +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL1_dft 0xFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL0 0x103C +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL0_dft 0xFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES04 0x103D +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES04_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES03 0x103E +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES03_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES02 0x103F +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES02_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES01 0x1040 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES01_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES00 0x1041 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES00_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES14 0x1042 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES14_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES13 0x1043 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES13_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES12 0x1044 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES12_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES11 0x1045 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES11_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES10 0x1046 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES10_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL00 0x1047 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL00_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL01 0x1048 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL01_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL02 0x1049 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL02_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL03 0x104A +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL03_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL10 0x104B +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL10_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL11 0x104C +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL11_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL12 0x104D +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL12_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL13 0x104E +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL13_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_VCOBIAS 0x104F +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_VCOBIAS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_STATUS 0x1050 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_STATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_RESOLUTION 0x1057 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_RESOLUTION_dft 0x3 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_CONTROL 0x1059 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_CONTROL_dft 0x2098 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTERRUPT 0x105B +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTSTATUS 0x105C +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTSTATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTENABLE 0x105D +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTENABLE_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTERRUPTZ 0x105E +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTERRUPTZ_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXELST0_Control 0x106E +#define CS4224_PP_LINE_SDS_COMMON_RXELST0_Control_dft 0x2 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Cfg 0x106F +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Cfg_dft 0x2000 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Ctrl 0x1070 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Ctrl_dft 0xC +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Count1 0x1071 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Count1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Count0 0x1072 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Count0_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_INTERRUPT 0x1073 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_INTSTATUS 0x1074 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_INTSTATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_RESET 0x1077 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_RESET_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_EN 0x1078 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_EN_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR0 0x1079 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR0_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR1 0x107A +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_NUMERATOR0 0x107D +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_NUMERATOR0_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_NUMERATOR1 0x107E +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_NUMERATOR1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_WIDTH 0x1081 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_WIDTH_dft 0xA +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_INTDIV 0x1082 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_INTDIV_dft 0x1919 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_STAGE_EN 0x1083 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_STAGE_EN_dft 0x408 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0 0x1084 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0_dft 0xCCCC +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1 0x1085 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1_dft 0xCC +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE2PRELOAD0 0x1086 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE2PRELOAD0_dft 0xCCCC +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE1PRELOAD0 0x1088 +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE1PRELOAD0_dft 0xCCCC +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE1PRELOAD1 0x1089 +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE1PRELOAD1_dft 0xCC +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0 0x108A +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0_dft 0xCCCC +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_DITHER 0x108D +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_DITHER_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_TX0_Config 0x108E +#define CS4224_PP_LINE_SDS_COMMON_TX0_Config_dft 0x18 +#define CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x108F +#define CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA_dft 0x814 +#define CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x1090 +#define CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH 0x1091 +#define CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_STX0_MISC 0x1092 +#define CS4224_PP_LINE_SDS_COMMON_STX0_MISC_dft 0x33 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Cfg 0x1096 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Cfg_dft 0x2000 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Ctrl 0x1097 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Ctrl_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Fixed0_Pattern1 0x1098 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Fixed0_Pattern1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_TXELST0_Control 0x109D +#define CS4224_PP_LINE_SDS_COMMON_TXELST0_Control_dft 0x2 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1 0x10A1 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2 0x10A2 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2_dft 0x40 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4 0x10A4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4_dft 0x81F0 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE 0x10A5 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB 0x10A6 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB_dft 0xD +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB 0x10A7 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB_dft 0xDFFF +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL1 0x10A8 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL2 0x10A9 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL2_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_BIAS1 0x10AA +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_BIAS1_dft 0x5555 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG 0x10AE +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG_dft 0x441 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_MONCTRL 0x10B1 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_MONCTRL_dft 0x2000 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG 0x10B2 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG_dft 0x607 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_CONFIG 0x10B4 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_CONFIG_dft 0x10 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_TUNE 0x10B5 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_TUNE_dft 0x404 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVERCML_TUNE 0x10B6 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVERCML_TUNE_dft 0x404 +#define CS4224_PP_LINE_SDS_COMMON_Int 0x10BA +#define CS4224_PP_LINE_SDS_COMMON_Int_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_IntEn 0x10BB +#define CS4224_PP_LINE_SDS_COMMON_IntEn_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKDi 0x10C7 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKDi_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKDe 0x10C8 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKDe_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR 0x1220 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1 0x1221 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0 0x1222 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_PC_SHADOW 0x1223 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_PC_SHADOW_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW 0x1224 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS 0x1225 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_dft 0x8 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_PC 0x1228 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_PC_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_IX 0x1229 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_IX_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_BASE3_INST 0x1233 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_BASE3_INST_dft 0x3 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_ENABLE 0x1234 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_ENABLE_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB 0x1235 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft 0x1E0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB 0x1236 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_STATUS 0x1237 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_STATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR 0x1238 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_SEL 0x1239 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_SEL_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_LSB 0x123A +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_MSB 0x123B +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB 0x123C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_MSB 0x123D +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MU_VALUE 0x1245 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MU_VALUE_dft 0xF0F +#define CS4224_PP_LINE_SDS_DSP_MSEQ_LEAK_INTVL_AGC 0x1247 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_LEAK_INTVL_AGC_dft 0x40 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_LEAK_INTVL_DFE 0x1248 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_LEAK_INTVL_DFE_dft 0x40 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_INIT_SEL 0x1249 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_INIT_SEL_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_FLOAT 0x124C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_FLOAT_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ1 0x125E +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ2 0x125F +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ2_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN0 0x1262 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN0_dft 0x1FF +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN1 0x1263 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN1_dft 0x1FF +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN2 0x1264 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN2_dft 0x1FF +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL 0x1265 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL_dft 0x20 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_SLICER 0x1266 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_SLICER_dft 0x80 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_AGC_MISC 0x1268 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_AGC_MISC_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_AGC_GAIN 0x1269 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_AGC_GAIN_dft 0x7 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_CTRL 0x126C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_CTRL_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_ZEROS_LSB 0x126D +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_ZEROS_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_LSB 0x1273 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_MSB 0x1274 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES 0x1275 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES_dft 0x30 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_LSB 0x1280 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_MSB 0x1281 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_LSB 0x1282 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_MSB 0x1283 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_LSB 0x1284 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_MSB 0x1285 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE3_LSB 0x1286 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE3_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE3_MSB 0x1287 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE3_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_LSB 0x1288 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_MSB 0x1289 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE5_LSB 0x128A +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE5_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE5_MSB 0x128B +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE5_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_LSB 0x128C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_MSB 0x128D +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_LSB 0x128E +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_MSB 0x128F +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE8_LSB 0x1290 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE8_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE8_MSB 0x1291 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE8_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_LSB 0x1292 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_MSB 0x1293 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE10_LSB 0x1294 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE10_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE10_MSB 0x1295 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE10_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_LSB 0x1296 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_MSB 0x1297 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB 0x1298 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB 0x1299 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_LSB 0x129A +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_MSB 0x129B +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE14_LSB 0x129C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE14_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE15_MSB 0x129F +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE15_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE16_LSB 0x12A0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE16_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_LSB 0x12A4 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_MSB 0x12A5 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE19_LSB 0x12A6 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE19_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_LSB 0x12A8 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_MSB 0x12A9 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_LSB 0x12AA +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB 0x12AB +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE22_LSB 0x12AC +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE22_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE22_MSB 0x12AD +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE22_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE23_LSB 0x12AE +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE23_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE23_MSB 0x12AF +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE23_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_LSB 0x12B0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_MSB 0x12B1 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE25_LSB 0x12B2 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE25_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE25_MSB 0x12B3 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE25_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_LSB 0x12B4 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB 0x12B5 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE27_LSB 0x12B6 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE27_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE27_MSB 0x12B7 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE27_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE28_LSB 0x12B8 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE28_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE28_MSB 0x12B9 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE28_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE0_0 0x1320 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE0_0_dft 0xA0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE0_1 0x1321 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE0_1_dft 0xF0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE1_0 0x1324 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE1_0_dft 0xE0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE1_1 0x1325 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE1_1_dft 0xF8 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE2_0 0x1328 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE2_0_dft 0xF0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE2_1 0x1329 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE2_1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE3_0 0x132C +#define CS4224_PP_LINE_SDS_DSP_IC_DFE3_0_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE3_1 0x132D +#define CS4224_PP_LINE_SDS_DSP_IC_DFE3_1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE4_0 0x132E +#define CS4224_PP_LINE_SDS_DSP_IC_DFE4_0_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE4_1 0x132F +#define CS4224_PP_LINE_SDS_DSP_IC_DFE4_1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_ENABLE 0x1343 +#define CS4224_PP_LINE_SDS_DSP_ENABLE_dft 0x4 +#define CS4224_PP_LINE_SDS_DSP_COEF_SATURATED_INT 0x1354 +#define CS4224_PP_LINE_SDS_DSP_COEF_SATURATED_INT_dft 0x0 +#define CS4224_PP_LINE_GIGEPCS_LINE_CONTROL 0x1460 +#define CS4224_PP_LINE_GIGEPCS_LINE_CONTROL_dft 0x140 +#define CS4224_PP_LINE_GIGEPCS_LINE_STATUS 0x1461 +#define CS4224_PP_LINE_GIGEPCS_LINE_STATUS_dft 0x9 +#define CS4224_PP_LINE_GIGEPCS_INT_LINE_PCS1GE_INTERRUPT 0x1480 +#define CS4224_PP_LINE_GIGEPCS_INT_LINE_PCS1GE_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_GIGEPCS_INT_LINE_PCS1GE_INTSTATUS 0x1482 +#define CS4224_PP_LINE_GIGEPCS_INT_LINE_PCS1GE_INTSTATUS_dft 0x0 +#define CS4224_PP_LINE_EGPCS_RX_MODE 0x14A0 +#define CS4224_PP_LINE_EGPCS_RX_MODE_dft 0x8003 +#define CS4224_PP_LINE_EGPCS_RX_INTERRUPT 0x14A4 +#define CS4224_PP_LINE_EGPCS_RX_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_EGPCS_RX_INTSTATUS 0x14A6 +#define CS4224_PP_LINE_EGPCS_RX_INTSTATUS_dft 0x0 +#define CS4224_PP_LINE_EGPCS_TX_MODE 0x14B0 +#define CS4224_PP_LINE_EGPCS_TX_MODE_dft 0x8001 +#define CS4224_PP_LINE_EGPCS_TX_INTERRUPT 0x14B5 +#define CS4224_PP_LINE_EGPCS_TX_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_XGPCS_TX_TXCNTRL 0x14C0 +#define CS4224_PP_LINE_XGPCS_TX_TXCNTRL_dft 0x8002 +#define CS4224_PP_LINE_XGPCS_RX_RXCNTRL 0x14E0 +#define CS4224_PP_LINE_XGPCS_RX_RXCNTRL_dft 0xD000 +#define CS4224_PP_LINE_XGPCS_RX_RXSTATUS 0x14E1 +#define CS4224_PP_LINE_XGPCS_RX_RXSTATUS_dft 0x0 +#define CS4224_PP_LINE_XGPCS_RX_RXINT 0x14E2 +#define CS4224_PP_LINE_XGPCS_RX_RXINT_dft 0x0 +#define CS4224_PP_LINE_AN_TX_ENABLE 0x1500 +#define CS4224_PP_LINE_AN_TX_ENABLE_dft 0x0 +#define CS4224_PP_LINE_AN_TX_COMPLETE_STATUS 0x1505 +#define CS4224_PP_LINE_AN_TX_COMPLETE_STATUS_dft 0x0 +#define CS4224_PP_LINE_AN_TX_AN_COMPLETE_STATUS_INT 0x1506 +#define CS4224_PP_LINE_AN_TX_AN_COMPLETE_STATUS_INT_dft 0x0 +#define CS4224_PP_LINE_AN_TX_ADV_ABILITY 0x150C +#define CS4224_PP_LINE_AN_TX_ADV_ABILITY_dft 0x0 +#define CS4224_PP_LINE_AN_TX_TECH_ABILITY_1 0x150D +#define CS4224_PP_LINE_AN_TX_TECH_ABILITY_1_dft 0x0 +#define CS4224_PP_LINE_AN_TX_BP_STATUS 0x151B +#define CS4224_PP_LINE_AN_TX_BP_STATUS_dft 0x1 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMEOUT0 0x1523 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMEOUT0_dft 0x17C8 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMER_THRES1 0x1524 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMER_THRES1_dft 0x3B9 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMER_THRES0 0x1525 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMER_THRES0_dft 0xACA0 +#define CS4224_PP_LINE_AN_TX_ABILITY_DETECT_TIMER_ENABLE 0x152A +#define CS4224_PP_LINE_AN_TX_ABILITY_DETECT_TIMER_ENABLE_dft 0x0 +#define CS4224_PP_LINE_AN_TX_MAIN_INT 0x152D +#define CS4224_PP_LINE_AN_TX_MAIN_INT_dft 0x0 +#define CS4224_PP_LINE_AN_TX_MAIN_INTS 0x152F +#define CS4224_PP_LINE_AN_TX_MAIN_INTS_dft 0x0 +#define CS4224_PP_LINE_AN_TX_TX_AFIFO_INT 0x1531 +#define CS4224_PP_LINE_AN_TX_TX_AFIFO_INT_dft 0x0 +#define CS4224_PP_LINE_AN_TX_ARBITRATOR_STATE 0x1536 +#define CS4224_PP_LINE_AN_TX_ARBITRATOR_STATE_dft 0x0 +#define CS4224_PP_LINE_AN_RX_PAGE_RECEIVED 0x1545 +#define CS4224_PP_LINE_AN_RX_PAGE_RECEIVED_dft 0x0 +#define CS4224_PP_LINE_AN_RX_LP_ABILITY_1 0x1546 +#define CS4224_PP_LINE_AN_RX_LP_ABILITY_1_dft 0x0 +#define CS4224_PP_LINE_AN_RX_LP_ABILITY_2 0x1547 +#define CS4224_PP_LINE_AN_RX_LP_ABILITY_2_dft 0x0 +#define CS4224_PP_LINE_AN_RX_MAIN_INT 0x155A +#define CS4224_PP_LINE_AN_RX_MAIN_INT_dft 0x0 +#define CS4224_PP_LINE_AN_RX_RX_AFIFO_INT 0x155E +#define CS4224_PP_LINE_AN_RX_RX_AFIFO_INT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_ENABLE 0x1580 +#define CS4224_PP_LINE_TP_TX_ENABLE_dft 0x0 +#define CS4224_PP_LINE_TP_TX_TX_RX_RESET 0x1581 +#define CS4224_PP_LINE_TP_TX_TX_RX_RESET_dft 0x3 +#define CS4224_PP_LINE_TP_TX_BITSWAP 0x1583 +#define CS4224_PP_LINE_TP_TX_BITSWAP_dft 0x1 +#define CS4224_PP_LINE_TP_TX_TRAINING 0x1586 +#define CS4224_PP_LINE_TP_TX_TRAINING_dft 0x0 +#define CS4224_PP_LINE_TP_TX_TRAINING_INT 0x1588 +#define CS4224_PP_LINE_TP_TX_TRAINING_INT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_TRAINING_INTS 0x158A +#define CS4224_PP_LINE_TP_TX_TRAINING_INTS_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMEOUT1 0x158C +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMEOUT1_dft 0x950 +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMEOUT0 0x158D +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMEOUT0_dft 0x2F90 +#define CS4224_PP_LINE_TP_TX_WAIT_TIMEOUT 0x158E +#define CS4224_PP_LINE_TP_TX_WAIT_TIMEOUT_dft 0x64 +#define CS4224_PP_LINE_TP_TX_ADDITIONAL_FRAMES 0x158F +#define CS4224_PP_LINE_TP_TX_ADDITIONAL_FRAMES_dft 0x2 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_MAX_LIMIT 0x1590 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_MAX_LIMIT_dft 0x30 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_MAX_LIMIT 0x1591 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_MAX_LIMIT_dft 0x30 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_MAX_LIMIT 0x1592 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_MAX_LIMIT_dft 0x30 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_MIN_LIMIT 0x1593 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_MIN_LIMIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_MIN_LIMIT 0x1594 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_MIN_LIMIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_MIN_LIMIT 0x1595 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_MIN_LIMIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_INIT 0x1596 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_INIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_INIT 0x1597 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_INIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_INIT 0x1598 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_INIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_PRESET_COEFF_OVERRIDE 0x1599 +#define CS4224_PP_LINE_TP_TX_PRESET_COEFF_OVERRIDE_dft 0x0 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_PRESET 0x159A +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_PRESET_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_PRESET 0x159B +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_PRESET_dft 0x0 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_PRESET 0x159C +#define CS4224_PP_LINE_TP_TX_POST_COEFF_PRESET_dft 0x0 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_START 0x159D +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_START_dft 0x5 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_START 0x159E +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_START_dft 0x23 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_START 0x159F +#define CS4224_PP_LINE_TP_TX_POST_COEFF_START_dft 0x24 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF 0x15A0 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF 0x15A1 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_dft 0x0 +#define CS4224_PP_LINE_TP_TX_POST_COEFF 0x15A2 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_dft 0x0 +#define CS4224_PP_LINE_TP_TX_COEFF_STEP_VALUE 0x15A3 +#define CS4224_PP_LINE_TP_TX_COEFF_STEP_VALUE_dft 0x111 +#define CS4224_PP_LINE_TP_TX_LD_COEFF_UPDATE_CTRL 0x15A4 +#define CS4224_PP_LINE_TP_TX_LD_COEFF_UPDATE_CTRL_dft 0x0 +#define CS4224_PP_LINE_TP_TX_FC_OPTIONS 0x15A8 +#define CS4224_PP_LINE_TP_TX_FC_OPTIONS_dft 0x0 +#define CS4224_PP_LINE_TP_TX_ENCODER_STATE 0x15A9 +#define CS4224_PP_LINE_TP_TX_ENCODER_STATE_dft 0x0 +#define CS4224_PP_LINE_TP_TX_TRAINING_STATE 0x15AA +#define CS4224_PP_LINE_TP_TX_TRAINING_STATE_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMER_EN 0x15AF +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMER_EN_dft 0x1 +#define CS4224_PP_LINE_TP_RX_BITSWAP 0x15C0 +#define CS4224_PP_LINE_TP_RX_BITSWAP_dft 0x1 +#define CS4224_PP_LINE_TP_RX_REMOTE_RX_READY 0x15C1 +#define CS4224_PP_LINE_TP_RX_REMOTE_RX_READY_dft 0x113 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_INT 0x15C2 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_INT_dft 0x0 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_INTS 0x15C4 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_INTS_dft 0x0 +#define CS4224_PP_LINE_TP_RX_FM_DETECT_STATE 0x15C9 +#define CS4224_PP_LINE_TP_RX_FM_DETECT_STATE_dft 0x0 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_STATE 0x15CA +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_STATE_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_RESET 0x1600 +#define CS4224_PP_LINE_KR_FEC_TX_RESET_dft 0x1 +#define CS4224_PP_LINE_KR_FEC_TX_STATUS 0x1602 +#define CS4224_PP_LINE_KR_FEC_TX_STATUS_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_STATS_CONTROL 0x160A +#define CS4224_PP_LINE_KR_FEC_TX_STATS_CONTROL_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_STATS_TX_BLK_TOTAL1 0x160B +#define CS4224_PP_LINE_KR_FEC_TX_STATS_TX_BLK_TOTAL1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_STATS_TX_BLK_TOTAL0 0x160C +#define CS4224_PP_LINE_KR_FEC_TX_STATS_TX_BLK_TOTAL0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_INT 0x160D +#define CS4224_PP_LINE_KR_FEC_TX_INT_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_RESET 0x1640 +#define CS4224_PP_LINE_KR_FEC_RX_RESET_dft 0x1 +#define CS4224_PP_LINE_KR_FEC_RX_STATUS 0x1642 +#define CS4224_PP_LINE_KR_FEC_RX_STATUS_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_CONTROL 0x1644 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_CONTROL_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_TOTAL1 0x1645 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_TOTAL1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_TOTAL0 0x1646 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_TOTAL0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_CORR1 0x1647 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_CORR1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_CORR0 0x1648 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_CORR0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_UNCORR1 0x1649 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_UNCORR1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_UNCORR0 0x164A +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_UNCORR0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ZERO_ERRS1 0x164B +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ZERO_ERRS1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ZERO_ERRS0 0x164C +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ZERO_ERRS0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ONE_ERRS1 0x164D +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ONE_ERRS1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ONE_ERRS0 0x164E +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ONE_ERRS0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_INT 0x165F +#define CS4224_PP_LINE_KR_FEC_RX_INT_dft 0x0 +#define CS4224_PP_LINE_MCAN_RESET 0x1680 +#define CS4224_PP_LINE_MCAN_RESET_dft 0x1 +#define CS4224_PP_HOST_HOSTMISC_SOFT_RESET 0x1800 +#define CS4224_PP_HOST_HOSTMISC_SOFT_RESET_dft 0x2 +#define CS4224_PP_HOST_HOSTMISC_MPIF_RESET_DOTREG 0x1801 +#define CS4224_PP_HOST_HOSTMISC_MPIF_RESET_DOTREG_dft 0x3 +#define CS4224_PP_HOST_HOSTMISC_GIGEPCS_SOFT_RESET 0x1802 +#define CS4224_PP_HOST_HOSTMISC_GIGEPCS_SOFT_RESET_dft 0x1 +#define CS4224_PP_HOST_HOSTMISC_FUNCEN 0x1803 +#define CS4224_PP_HOST_HOSTMISC_FUNCEN_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_CLKEN 0x1804 +#define CS4224_PP_HOST_HOSTMISC_CLKEN_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_MATE_SELECT 0x1806 +#define CS4224_PP_HOST_HOSTMISC_MATE_SELECT_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_MSEQCLKCTRL 0x1807 +#define CS4224_PP_HOST_HOSTMISC_MSEQCLKCTRL_dft 0x4 +#define CS4224_PP_HOST_HOSTMISC_OVERRIDE_EN 0x1810 +#define CS4224_PP_HOST_HOSTMISC_OVERRIDE_EN_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_INTERRUPT 0x1811 +#define CS4224_PP_HOST_HOSTMISC_INTERRUPT_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_INTENABLE 0x1812 +#define CS4224_PP_HOST_HOSTMISC_INTENABLE_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RX0_Config 0x1820 +#define CS4224_PP_HOST_SDS_COMMON_RX0_Config_dft 0x18 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG 0x1821 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL 0x1823 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL_dft 0x3005 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKOUT_CTRL 0x1824 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKOUT_CTRL_dft 0x2FF +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CPA 0x1827 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CPA_dft 0x77 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_IBIAS_TUNE 0x1829 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_IBIAS_TUNE_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_RBIAS_TUNE 0x182A +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_RBIAS_TUNE_dft 0x44 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_SPARE 0x182F +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_SPARE_dft 0xE0F0 +#define CS4224_PP_HOST_SDS_COMMON_RXVCO0_CONTROL 0x1833 +#define CS4224_PP_HOST_SDS_COMMON_RXVCO0_CONTROL_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXVCO0_ALTCT_STATUS 0x1837 +#define CS4224_PP_HOST_SDS_COMMON_RXVCO0_ALTCT_STATUS_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_CONTROL 0x1859 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_CONTROL_dft 0x2098 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTERRUPT 0x185B +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTERRUPT_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTSTATUS 0x185C +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTSTATUS_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTENABLE 0x185D +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTENABLE_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTERRUPTZ 0x185E +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTERRUPTZ_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXELST0_Control 0x186E +#define CS4224_PP_HOST_SDS_COMMON_RXELST0_Control_dft 0x2 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Cfg 0x186F +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Cfg_dft 0x2000 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Ctrl 0x1870 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Ctrl_dft 0xC +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Count1 0x1871 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Count1_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Count0 0x1872 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Count0_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_INTERRUPT 0x1873 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_INTERRUPT_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_INTSTATUS 0x1874 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_INTSTATUS_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_RESET 0x1877 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_RESET_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_EN 0x1878 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_EN_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR0 0x1879 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR0_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR1 0x187A +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR1_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_NUMERATOR0 0x187D +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_NUMERATOR0_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_NUMERATOR1 0x187E +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_NUMERATOR1_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_WIDTH 0x1881 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_WIDTH_dft 0xA +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_INTDIV 0x1882 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_INTDIV_dft 0x1919 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_STAGE_EN 0x1883 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_STAGE_EN_dft 0x408 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0 0x1884 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0_dft 0xCCCC +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1 0x1885 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1_dft 0xCC +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE1PRELOAD0 0x1888 +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE1PRELOAD0_dft 0xCCCC +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE1PRELOAD1 0x1889 +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE1PRELOAD1_dft 0xCC +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0 0x188A +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0_dft 0xCCCC +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_DITHER 0x188D +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_DITHER_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_TX0_Config 0x188E +#define CS4224_PP_HOST_SDS_COMMON_TX0_Config_dft 0x18 +#define CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x188F +#define CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA_dft 0x814 +#define CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x1890 +#define CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH 0x1891 +#define CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_STX0_MISC 0x1892 +#define CS4224_PP_HOST_SDS_COMMON_STX0_MISC_dft 0x33 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Cfg 0x1896 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Cfg_dft 0x2000 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Ctrl 0x1897 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Ctrl_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Fixed0_Pattern1 0x1898 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Fixed0_Pattern1_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_TXELST0_Control 0x189D +#define CS4224_PP_HOST_SDS_COMMON_TXELST0_Control_dft 0x2 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1 0x18A1 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG2 0x18A2 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG2_dft 0x40 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG4 0x18A4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG4_dft 0x81F0 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_RTUNE 0x18A5 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_RTUNE_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB 0x18A6 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB_dft 0xD +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB 0x18A7 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB_dft 0xDFFF +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG 0x18AE +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG_dft 0x441 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG 0x18B2 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG_dft 0x607 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_CONFIG 0x18B4 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_CONFIG_dft 0x10 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE 0x18B5 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE_dft 0x404 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE 0x18B6 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE_dft 0x404 +#define CS4224_PP_HOST_SDS_COMMON_Int 0x18BA +#define CS4224_PP_HOST_SDS_COMMON_Int_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_IntEn 0x18BB +#define CS4224_PP_HOST_SDS_COMMON_IntEn_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKDi 0x18C7 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKDi_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKDe 0x18C8 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKDe_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_CR 0x1A20 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_CR_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_D1 0x1A21 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_D1_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_D0 0x1A22 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_D0_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_PC_SHADOW 0x1A23 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_PC_SHADOW_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_SHADOW 0x1A24 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_SHADOW_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS 0x1A25 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_dft 0x8 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_PC 0x1A28 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_PC_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_IX 0x1A29 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_IX_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_BASE3_INST 0x1A33 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_BASE3_INST_dft 0x3 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_ENABLE 0x1A34 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_ENABLE_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB 0x1A35 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft 0x1E0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_STATUS 0x1A37 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_STATUS_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_BANK_SELECTOR 0x1A38 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_BANK_SELECTOR_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_SEL 0x1A39 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_SEL_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_LSB 0x1A3A +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_MSB 0x1A3B +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_LSB 0x1A3C +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_MSB 0x1A3D +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_CAL_RX_PHSEL 0x1A65 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_CAL_RX_PHSEL_dft 0x20 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SERDES 0x1A75 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SERDES_dft 0x30 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE0_LSB 0x1A80 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE0_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE6_MSB 0x1A8D +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE6_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_LSB 0x1A98 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_MSB 0x1A99 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE14_LSB 0x1A9C +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE14_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE15_MSB 0x1A9F +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE15_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE20_MSB 0x1AA9 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE20_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE22_LSB 0x1AAC +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE22_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE22_MSB 0x1AAD +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE22_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE24_MSB 0x1AB1 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE24_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE25_LSB 0x1AB2 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE25_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE25_MSB 0x1AB3 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE25_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE26_MSB 0x1AB5 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE26_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE28_MSB 0x1AB9 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE28_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_COEF_SATURATED_INT 0x1B54 +#define CS4224_PP_HOST_SDS_DSP_COEF_SATURATED_INT_dft 0x0 +#define CS4224_PP_HOST_GIGEPCS_INT_HOST_PCS1GE_INTERRUPT 0x1C80 +#define CS4224_PP_HOST_GIGEPCS_INT_HOST_PCS1GE_INTERRUPT_dft 0x0 +#define CS4224_PP_HOST_GIGEPCS_INT_HOST_PCS1GE_INTSTATUS 0x1C82 +#define CS4224_PP_HOST_GIGEPCS_INT_HOST_PCS1GE_INTSTATUS_dft 0x0 +#define CS4224_PP_CLKMON_ING_CLKSEL 0x1D00 +#define CS4224_PP_CLKMON_ING_CLKSEL_dft 0x7F +#define CS4224_PP_CLKMON_ING_CTRL 0x1D01 +#define CS4224_PP_CLKMON_ING_CTRL_dft 0x110 +#define CS4224_PP_CLKMON_ING_DURATION 0x1D02 +#define CS4224_PP_CLKMON_ING_DURATION_dft 0x0 +#define CS4224_PP_CLKMON_ING_STATUS 0x1D03 +#define CS4224_PP_CLKMON_ING_STATUS_dft 0x0 +#define CS4224_PP_CLKMON_ING_COUNT1 0x1D04 +#define CS4224_PP_CLKMON_ING_COUNT1_dft 0x0 +#define CS4224_PP_CLKMON_ING_COUNT0 0x1D05 +#define CS4224_PP_CLKMON_ING_COUNT0_dft 0x0 +#define CS4224_PP_CLKMON_ING_MINTHRESH1 0x1D06 +#define CS4224_PP_CLKMON_ING_MINTHRESH1_dft 0x0 +#define CS4224_PP_CLKMON_ING_MINTHRESH0 0x1D07 +#define CS4224_PP_CLKMON_ING_MINTHRESH0_dft 0x0 +#define CS4224_PP_CLKMON_ING_MAXTHRESH1 0x1D08 +#define CS4224_PP_CLKMON_ING_MAXTHRESH1_dft 0x0 +#define CS4224_PP_CLKMON_ING_MAXTHRESH0 0x1D09 +#define CS4224_PP_CLKMON_ING_MAXTHRESH0_dft 0x0 +#define CS4224_PP_CLKMON_EGR_CLKSEL 0x1D10 +#define CS4224_PP_CLKMON_EGR_CLKSEL_dft 0x7F +#define CS4224_PP_CLKMON_EGR_CTRL 0x1D11 +#define CS4224_PP_CLKMON_EGR_CTRL_dft 0x110 +#define CS4224_PP_CLKMON_EGR_DURATION 0x1D12 +#define CS4224_PP_CLKMON_EGR_DURATION_dft 0x0 +#define CS4224_PP_CLKMON_EGR_STATUS 0x1D13 +#define CS4224_PP_CLKMON_EGR_STATUS_dft 0x0 +#define CS4224_PP_CLKMON_EGR_COUNT1 0x1D14 +#define CS4224_PP_CLKMON_EGR_COUNT1_dft 0x0 +#define CS4224_PP_CLKMON_EGR_COUNT0 0x1D15 +#define CS4224_PP_CLKMON_EGR_COUNT0_dft 0x0 +#define CS4224_PP_CLKMON_EGR_MINTHRESH1 0x1D16 +#define CS4224_PP_CLKMON_EGR_MINTHRESH1_dft 0x0 +#define CS4224_PP_CLKMON_EGR_MINTHRESH0 0x1D17 +#define CS4224_PP_CLKMON_EGR_MINTHRESH0_dft 0x0 +#define CS4224_PP_CLKMON_EGR_MAXTHRESH1 0x1D18 +#define CS4224_PP_CLKMON_EGR_MAXTHRESH1_dft 0x0 +#define CS4224_PP_CLKMON_EGR_MAXTHRESH0 0x1D19 +#define CS4224_PP_CLKMON_EGR_MAXTHRESH0_dft 0x0 +#define CS4224_EEPROM_LOADER_STATUS 0x5001 +#define CS4224_EEPROM_LOADER_STATUS_dft 0x0 +#define CS4224_EEPROM_MICRO_ACCESS_CONTROL 0x5005 +#define CS4224_EEPROM_MICRO_ACCESS_CONTROL_dft 0x0 +#define CS4224_EEPROM_MICRO_ACCESS_STATUS 0x5006 +#define CS4224_EEPROM_MICRO_ACCESS_STATUS_dft 0x0 + +/* bit masks */ +#define CS_BIT0 0x0001 +#define CS_BIT1 0x0002 +#define CS_BIT2 0x0004 +#define CS_BIT3 0x0008 +#define CS_BIT4 0x0010 +#define CS_BIT5 0x0020 +#define CS_BIT6 0x0040 +#define CS_BIT7 0x0080 +#define CS_BIT8 0x0100 +#define CS_BIT9 0x0200 +#define CS_BIT10 0x0400 +#define CS_BIT11 0x0800 +#define CS_BIT12 0x1000 +#define CS_BIT13 0x2000 +#define CS_BIT14 0x4000 +#define CS_BIT15 0x8000 + +/* bit masks for MSB registers */ +#define CS_MSB_BIT16 0x0001 +#define CS_MSB_BIT17 0x0002 +#define CS_MSB_BIT18 0x0004 +#define CS_MSB_BIT19 0x0008 +#define CS_MSB_BIT20 0x0010 +#define CS_MSB_BIT21 0x0020 +#define CS_MSB_BIT22 0x0040 +#define CS_MSB_BIT23 0x0080 +#define CS_MSB_BIT24 0x0100 +#define CS_MSB_BIT25 0x0200 +#define CS_MSB_BIT26 0x0400 +#define CS_MSB_BIT27 0x0800 +#define CS_MSB_BIT28 0x1000 +#define CS_MSB_BIT29 0x2000 +#define CS_MSB_BIT30 0x4000 +#define CS_MSB_BIT31 0x8000 + +unsigned int CS_ABS(int value); + +void *CS_MEMSET(void *p, int c, int n); +void *CS_MEMCPY(void *p, const void *src, int n); +int CS_STRLEN(const char *s); +char *CS_STRCAT(char *dest, const char *source); +char *CS_STRNCPY(char *dest, const char *source, int count); + +#define CS_IF_SET(val, mask) (((val) & (mask)) != 0) +#define CS_IF_ALL_SET(val, mask) (((val) & (mask)) == mask) +#define CS_IF_CLR(val, mask) (((val) & (mask)) == 0) +#define CS_SET(val, mask) (((val) | (mask))) +#define CS_CLR(val, mask) (((val) & ~(mask))) +#define CS_TOGGLE(val, mask) (((val) ^ (mask))) + +enum e_cs4224_kran_an_status_t { + CS4224_KRAN_AN_NOT_DONE, + CS4224_KRAN_AN_DONE, +}; + +struct cs4224_kran_advertised_config_t_s { + /* (A4) (4 x 10G) 40G Faceplate/Cable */ + unsigned short tech_cr4; + + /* (A3) (4 x 10G) 40G Backplane */ + unsigned short tech_kr4; + + /* (A2) 10G Backplane */ + unsigned short tech_kr; + + /* (A0) 1G Backplane */ + unsigned short tech_kx; + + /* (A1) (4 x 2.5G) 10G Backplane */ + unsigned short tech_kx4; + + /* (F0) FEC Ability */ + unsigned short f0; + + /* (F1) FEC Requested */ + unsigned short f1; + + /* (C0) Link Partner Pause Ability */ + unsigned short pause_0; + + /* (C1) Link Partner Pause Ability */ + unsigned short pause_1; + + /* (D13) Remote Fault */ + unsigned short rf; +}; + +struct cs4224_kran_advanced_config_t_s { + /* Enable the line side fixed-phase override */ + unsigned char phase_or; + + /* Enable the host side fixed-phase override */ + unsigned char hphase_or; + + /* Enable the AN Ability Detect Timeout */ + unsigned char en_adt; + + /* Enable the TP Max Wait Timer */ + unsigned char en_mwt; + + /* Skip Auto-Negotiation */ + unsigned char skip_an; + + /* Skip Training */ + unsigned char skip_tp; + + /* Skip line side Phase Calibration */ + unsigned char skip_phsc; + + /* Enable Link Fail Inhibit Timer */ + unsigned char en_lfit; + + /* Enable AN Retries */ + unsigned char en_retry; + + /* Disable AN start */ + unsigned char dis_start; + + /* Enable DFE Power Savings */ + unsigned char en_pwrsv; + + /* Enable DFE */ + unsigned char en_dfe; + + /* Count Frames with Invalid Markers */ + unsigned char bad_mrkrs; + + /* Disable PCS Sync Checks in Mission Mode */ + unsigned char dis_sync; + /* Enable the tx squelch control in the egress (host->line) path */ + unsigned char sqlch_egr; + + /* Enable the tx squelch control in the ingress (line->host) path */ + unsigned char sqlch_ing; + + /* Enables the use of the ring oscillator VCO */ + unsigned char ring; + + /* Line side Fixed-phase value, used only when phase_or is TRUE */ + unsigned short phase_ov; + + /* Host side fixed-phase value, used only when hphase_or is TRUE */ + unsigned short hphase_ov; + + /* Number of Additional Frames to Send at the Start of SEND_DATA */ + unsigned short xtra_f; + + /* Iterations to Wait for PCS to Sync (multiply by 2^16) */ + unsigned short pcs_itr; + + /* 10G LFI Timeout */ + unsigned short lfi_10g; + + /* TP_TX maximum wait */ + unsigned short max_wait; + + /* LFI Threshold */ + unsigned short lfi_thres; + + /* 1G LFI timeout */ + unsigned short lfi_1g; + + /* Override the LINK_READY wait_timer */ + unsigned short wait_tmr; + + /* True = Main-cursor incremented to maximum, + * False=Main-cursor untouched + */ + unsigned char tpm0; + + /* True = Post-cursor adaptive calibration, + * False=Post-cursor incremented to maximum + */ + unsigned char tpm1; + + /* True = Send preset command at start */ + unsigned char tpm2; + + /* True = Send init command at start */ + unsigned char tpm3; + + /* True = Force local_rx_ready to True immediately */ + unsigned char tpm4; + + /* Always set to 'b000 */ + unsigned short tpm567; + + /* True = Enable pre/main/post Cursor Preset Values */ + unsigned char preset; + + /* True = Skip Rx data corruption */ + unsigned char tpm30; + + /* True = Invert Pre & Post cursor orientation (Leeds emulation mode) */ + unsigned char tpm31; + + /* True = calibrate if we lose lock */ + unsigned char jmp2cal; + + /* True = reference clock frequency is 106.25Mhz, + * set according to rules->ref_clk_rate + */ + unsigned char ref106; + + /* True = two-pass mode for optical links enabled */ + unsigned short two_pass_mode; + + /* True = disable FEC even when FEC is advertized and negotiated */ + unsigned short fec_bypass; + + /* Time to EDC converge in DFE mode, line side, + * range 0...0xffff, default 0x0180 + */ + unsigned short line_t_to_conv_dfe; + + /* Time to EDC converge in DFE mode, host side, + * range 0...0xffff, default 0x0240 + */ + unsigned short host_t_to_conv_dfe; + +}; + +struct cs4224_kran_config_t_s { + struct cs4224_kran_advertised_config_t_s advertised; + struct cs4224_kran_advanced_config_t_s advanced; +}; + +struct cs4224_kran_results_t_s { + /* Parallel detect */ + unsigned char bp_par_detect:1; + + /* (4 x 10G) 40G CR4 capability detect */ + unsigned char bp_40gcr4:1; + + /* (4 x 10G) 40G KR4 capability detect */ + unsigned char bp_40gkr4:1; + + /* 10G KR capability detect */ + unsigned char bp_10gkr:1; + + /* 1G KX capability detect */ + unsigned char bp_1000kx:1; + + /* (4 x 2.5G) 10G KX4 capability detect */ + unsigned char bp_10gkx4:1; + + /* FEC capability detect */ + unsigned char bp_fec:1; + + /* Remote Fault */ + unsigned char bp_rf:1; + + /* Pause ability */ + unsigned char bp_pause:3; +}; +extern unsigned int cs4224_max_num_ports; + +unsigned int CS4224_MAX_NUM_PORTS(void); +unsigned int CS4224_MAX_NUM_SLICES(unsigned int slice); +unsigned int CS4224_MAX_NUM_DIES(unsigned int slice); + +#define CS4224_RULE_DISABLED 0xFFFF +#define CS4224_MAX_NUM_CS4223_PORTS 4 /* 4 port duplex */ +#define CS4224_MAX_NUM_CS4224_PORTS 16 /* 16 port simplex */ +#define CS4224_MAX_NUM_CS4343_PORTS 8 /* 8 port duplex */ +#define CS4224_MAX_NUM_CS4221_PORTS 10 /* 10 port simplex */ +#define CS4224_MAX_NUM_CS4227_PORTS 2 /* 2 port duplex */ +#define CS4224_MAX_NUM_CS4210_PORTS 16 /* 16 port simplex */ +#define CS4224_MAX_NUM_CS4341_PORTS 8 /* 8 port duplex */ + +/* The number of available dies in the device */ +#define CS4224_MAX_NUM_CS4223_DIES 1 /* 4 port duplex */ +#define CS4224_MAX_NUM_CS4224_DIES 2 /* 16 port simplex */ +#define CS4224_MAX_NUM_CS4343_DIES 2 /* 8 port duplex */ +#define CS4224_MAX_NUM_CS4221_DIES 2 /* 10 port simplex */ +#define CS4224_MAX_NUM_CS4227_DIES 1 /* 2 port duplex */ +#define CS4224_MAX_NUM_CS4210_DIES 2 /* 16 port simplex */ +#define CS4224_MAX_NUM_CS4341_DIES 2 /* 8 port duplex */ + +/* The difference between line and host PP registers */ +#define CS4224_LINE_TO_HOST_OFFSET 0x0800 + +#define CS4224_REF_CLK_156p25 156250 /* kHz */ +#define CS4224_REF_CLK_155p52 155520 +#define CS4224_REF_CLK_106p25 106250 + +/* The preferred GLOBAL_MDIO_CONFIG value */ +#define CS4224_GLOBAL_MDIO_CONFIG_pref 0x78 + +/* Required or loaded ucode image bit map */ +enum e_cs4224_ucode_image { + CS4224_UCODE_IMAGE_NONE = 0x0, + CS4224_UCODE_IMAGE_KR = 0x1, + CS4224_UCODE_IMAGE_FC = 0x2, + CS4224_UCODE_IMAGE_ANY = 0x3, +}; + +/* Hardware ID numbers for the ASIC as defined in Efuse SKU */ +enum e_cs4224_hardware_id { + /* Undefined */ + CS4224_HW_UNDEF = 0, + + /* 4 port duplex */ + CS4224_HW_CS4223 = 0x0010, + + /* 16 port simplex */ + CS4224_HW_CS4224 = 0x0011, + + /* 8 port duplex */ + CS4224_HW_CS4343 = 0x0012, + + /* 10 port simplex */ + CS4224_HW_CS4221 = 0x0013, + + /* 2 port duplex */ + CS4224_HW_CS4227 = 0x0014, + + /* 16 port simplex, 15G only */ + CS4224_HW_CS4210 = 0x0015, + + /* 8 port duplex, 10G only */ + CS4224_HW_CS4341 = 0x0016 +}; + +/* Pre-defined target applications used + * with the cs4224_rules_set_default() method + * to setup default configurations + */ +enum e_cs4224_target_application { + /* Configure the device for 156.25MHz ref clock, 1.25GHz operation */ + CS4224_TARGET_APPLICATION_1G = 0, + + /* Configure the device for 156.25MHz ref clock, 5GHz operation */ + CS4224_TARGET_APPLICATION_5G, + + /* Configure the device for 156.25MHz ref clock, 7.5GHz operation */ + CS4224_TARGET_APPLICATION_7p5G, + + /* Configure the device for 156.25MHz ref clock, 8GHz operation */ + CS4224_TARGET_APPLICATION_8G, + + /* Configure the device for 156.25MHz ref clock, 8.5GHz operation */ + CS4224_TARGET_APPLICATION_8p5G, + + /* Configure the device for 156.25MHz ref clock, 10.3125GHz operation */ + CS4224_TARGET_APPLICATION_10G, + + /* Configure the device for 156.25MHz ref clock, 15GHz operation */ + CS4224_TARGET_APPLICATION_15G, + CS4224_TARGET_APPLICATION_10G_KR, + CS4224_TARGET_APPLICATION_40G_KR, + + /* Configure the device for KR-AN operation */ + CS4224_TARGET_APPLICATION_KRAN, + + /* Configure the device for FC-AN operation */ + CS4224_TARGET_APPLICATION_FCAN, + + /* Configure the device for 106.25MHz refclk, 14.025GHz FC */ + CS4224_TARGET_APPLICATION_16G_FC, + + /* Configure the device for 106.25MHz refclk, 10.51875GHz FC */ + CS4224_TARGET_APPLICATION_10G_FC, + + /* Configure the device for 106.25MHz refclk, 8.5GHz FC */ + CS4224_TARGET_APPLICATION_8G_FC, + + /* Configure the device for 106.25MHz refclk, 4.25GHz FC */ + CS4224_TARGET_APPLICATION_4G_FC, + + /* Configure the device for 106.25MHz refclk, 2.125GHz FC*/ + CS4224_TARGET_APPLICATION_2G_FC, + + /* Configure the device for 106.25MHz refclk, 1.0625GHz FC */ + CS4224_TARGET_APPLICATION_1G_FC, + + /* Configure the device for 156.25MHz refclk, 622.08MHz OC12 */ + CS4224_TARGET_APPLICATION_OC12 +}; + +#define e_cs4224_cfg_sides_t e_cs4224_datapath_dir_t + +/* Data-path direction and side selector */ +enum e_cs4224_datapath_dir_t { + /* Select the Line to Host path (Ingress) */ + CS4224_LINE_RX_TO_HOST_TX_DIR = 1, + + /* Configure the line side */ + CS4224_CFG_LINE_SIDE = 1, + + /* Select the Host to Line path (Egress) */ + CS4224_HOST_RX_TO_LINE_TX_DIR = 2, + + /* Configure the host side */ + CS4224_CFG_HOST_SIDE = 2, + + /* The channel is simplex; direction is picked automatically by API */ + CS4224_SIMPLEX_DIR = 3, + + /* Configure a simplex slice */ + CS4224_CFG_SIMPLEX = 3, +}; + +/* The supply voltage for the voltage monitor */ +enum e_cs4224_mon_vlt_supply { + /* 0.9V supply TX */ + CS4224_VLT_SUPPLY_0p9V = 0, + + /* 1.8V supply */ + CS4224_VLT_SUPPLY_1p8V = 1, +}; + +/* The EDC modes supported by the microcode */ +enum e_cs4224_edc_mode { + /* + * Disable the microcode. Does not disable the EDC. + * + * @{warning, + * This mode is not recommended and should not be used unless + * explicitly told to do so by Cortina + * } + */ + CS_HSIO_EDC_MODE_DISABLED = 0x0001, + + /* + * DFE mode meant for CX1 or direct attach compatible cables. + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied + * } + */ + CS_HSIO_EDC_MODE_CX1 = 0x0002, + + /* + * Non-DFE mode meant to support low channel loss applications. + * + * Short for 'short reach'. This mode is suitable for connecting to + * SR modules, very short on-board connections, or anything involving + * slow data rates. + * + * @{note, + * Although it's a fully adaptive mode, unlike DFE modes receiver tuning + * is required to maximize performance. See these rules: + * + * - rules.rx_if.dplx_line_eq (Duplex devices) + * - rules.rx_if.dplx_host_eq (Duplex devices) + * - rules.rx_if.splx_eq (Simplex devices) + * } + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 622Mbps ! 15Gbps ! API Optimized range + * } + * + */ + CS_HSIO_EDC_MODE_SR = 0x0004, + + /* + * DFE mode meant to support ZR modules. + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied + * } + */ + CS_HSIO_EDC_MODE_ZR = 0x0008, + + /* + * DFE mode meant to support DWDM modules. + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied + * } + */ + CS_HSIO_EDC_MODE_DWDM = 0x0010, + + /* + * DFE mode meant to support 9.8 to 12.5G data rates over a backplane. + * + * @{note, + * KR-AN DFE mode is supported through CS_HSIO_EDC_MODE_10G_BP, + * see KR-AN programming + * examples for more info. + * } + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied to improve + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied to improve + * } + */ + CS_HSIO_EDC_MODE_10G_BP = 0x0020, + + /* + * DFE mode meant to support 12.5 to 15G data rates over a backplane. + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 12.5Gbps ! <14Gbps ! Optional tuning could be applied. + * - 14Gbps ! 15Gbps ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_15G_BP = 0x0040, + + /* + * DFE mode meant to support 5 to 7.5G data rates over a backplane. + * + * @{note, + * CS_HSIO_EDC_MODE_5G_BP and CS_HSIO_EDC_MODE_7p5G_BP are functionally + * equivalent + * } + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 5.0Gbps ! 7.5Gbps ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_5G_BP = 0x0080, + + /* + * DFE mode meant to support 5 to 7.5G data rates over a backplane. + * + * @{note, + * CS_HSIO_EDC_MODE_5G_BP and CS_HSIO_EDC_MODE_7p5G_BP are functionally + * equivalent + * } + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 5.0Gbps ! 7.5Gbps ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_7p5G_BP = 0x0100, + + /* + * DFE mode meant to support 8 to 8.6G data rates over a backplane. + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 8.0Gbps ! 8.6Gbps ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_8p5G_BP = 0x0200, + + /* + * DFE mode for the line side on FC-AN connections. + * + * @{note, + * FC-AN SR/DFE mode on the line side is supported through + * CS_HSIO_EDC_MODE_FCAN, + * see FC-AN programming examples for more info. + * } + * + * @{table, + * -h Supported Data Rates + * -s Fibre Channel Rates ! Note + * - FC1, FC2, FC4, FC8, FC10, FC16 ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_FCAN = 0x0400, + + /* + * DFE mode meant for very specific 15G backplane applications. + * + * @{warning, + * Do not use unless advised to do so by a Cortina AE. + * } + */ + CS_HSIO_EDC_MODE_15G_BP_27dB = 0x0800, + + /* + * DFE mode meant for Single Mode Fibre with a Long Reach Module (SMLRM) + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied + * } + */ + CS_HSIO_EDC_MODE_SMLRM = 0x1000 +}; + +/* Settings used to compensate for trace loss on the board */ +enum e_cs4224_trace_loss { + /* For trace loss where trace loss <= 1dB */ + CS_HSIO_TRACE_LOSS_0dB, + + /* For trace loss where trace loss <= 2dB */ + CS_HSIO_TRACE_LOSS_1dB, + + /* For trace loss where 2dB < trace loss <= 3dB */ + CS_HSIO_TRACE_LOSS_2dB, + + /* For trace loss where 3dB < trace loss < 4dB */ + CS_HSIO_TRACE_LOSS_3dB, + + /* For trace loss where 4dB < trace loss <= 5dB */ + CS_HSIO_TRACE_LOSS_4dB, + + /* For trace loss where 5dB < trace loss <= 5.5dB */ + CS_HSIO_TRACE_LOSS_5dB, + + /* For trace loss where trace loss > 5.5dB */ + CS_HSIO_TRACE_LOSS_6dB, + + /* For trace loss where trace loss = 15dB */ + CS_HSIO_TRACE_LOSS_15dB, + + /* For trace loss where trace loss = 27dB */ + CS_HSIO_TRACE_LOSS_27dB, + + /* For CR4 cables */ + CS_HSIO_TRACE_LOSS_CR4, + + /* Special case for no-loss coax cables, for use in the lab */ + CS_HSIO_TRACE_LOSS_LAB, +}; + +/* Polarity Inversion bit map */ +enum e_cs4224_polarity_inv_t { + /* No polarity inversion */ + CS4224_POLARITY_INV_NONE = 0, + + /* Duplex host Tx driver polarity inversion */ + CS4224_POLARITY_INV_DPLX_HOST_TX = 1 << 0, + + /* Duplex line Tx driver polarity inversion */ + CS4224_POLARITY_INV_DPLX_LINE_TX = 1 << 1, + + /* Simplex Tx driver polarity inversion */ + CS4224_POLARITY_INV_SPLX_TX = 1 << 2, + + /* Duplex host Rx (digital, pre-FEC) polarity inversion */ + CS4224_POLARITY_INV_DPLX_HOST_RX = 1 << 3, + + /* Duplex line Rx (digital, pre-FEC) polarity inversion */ + CS4224_POLARITY_INV_DPLX_LINE_RX = 1 << 4, + + /* Simplex Rx (digital, pre-FEC) polarity inversion */ + CS4224_POLARITY_INV_SPLX_RX = 1 << 5, + +}; + +/* Determines which microsequencer to stall/un-stall */ +enum e_cs4224_mseq_id { + /* The simplex (line or host) microsequencer */ + CS4224_SPLX_MSEQ = 0, + + /* The duplex (line) microsequencer */ + CS4224_DPLX_LINE_MSEQ = 1, + + /* The duplex (host) microsequencer */ + CS4224_DPLX_HOST_MSEQ = 2, +}; + +/* Protection switch specific actions, note that for digital broadcast switching + * the 0 refers to the lower slice (even) of the protection pair, slice 1 the + * higher (odd). + */ +enum e_cs4224_switch_action_t { + /* disable switch */ + CS4224_SWITCH_DISABLE = 0, + + /* Duplex 2x2 switch from slices 0 to 1 and 1 to 0 bi-directionally */ + CS4224_SWITCH_DIGITAL_SWITCH_2x2 = 1, + /* Duplex 2x2 switch from slices 0 to 1 and 1 to 0 bi-directionally */ + CS4224_SWITCH_DUPLEX_SWITCH_2x2 = 1, + + /* Digital broadcast, Rx/Tx on slice 0 to 0 with line Tx only on 1 */ + CS4224_SWITCH_DIGITAL_BROADCAST_0_to_0 = 2, + /* Duplex broadcast, Rx/Tx on slice 0 to 0 with line Tx only on 1 */ + CS4224_SWITCH_DUPLEX_BROADCAST_0_to_0 = 2, + + /* Digital broadcast, Rx/Tx on slice 1 to 1 with line Tx only on 0 */ + CS4224_SWITCH_DIGITAL_BROADCAST_1_to_1 = 3, + CS4224_SWITCH_DUPLEX_BROADCAST_1_to_1 = 3, + + /* Digital broadcast, Rx/Tx on slice 0 to 1 with line Tx only on 0 */ + CS4224_SWITCH_DIGITAL_BROADCAST_0_to_1 = 4, + CS4224_SWITCH_DUPLEX_BROADCAST_0_to_1 = 4, + + /* Digital broadcast, Rx/Tx on slice 1 to 0 with line Tx only on 1 */ + CS4224_SWITCH_DIGITAL_BROADCAST_1_to_0 = 5, + CS4224_SWITCH_DUPLEX_BROADCAST_1_to_0 = 5, + + /* Simplex 2x2 switch of slice with mate */ + CS4224_SWITCH_SIMPLEX_SWITCH_2x2 = 6, + /* Analog 2x2 switch of slice with mate */ + CS4224_SWITCH_ANALOG_SWITCH_2x2 = 6, + + /* Simplex broadcast, transmits on slice and its mate */ + CS4224_SWITCH_SIMPLEX_BROADCAST = 7, + /* Analog broadcast, transmits on slice and its mate */ + CS4224_SWITCH_ANALOG_BROADCAST = 7, + +}; + +/* The CLKDIV_CTRL, SRX_DDIV_SEL dividers + * NOTE: There are accidentally two structures like this, the other is below + */ +enum e_cs4224_clkdiv_ddiv_t { + /* Rx serial clock div by 1 */ + CS4224_CLKDIV_DDIV_BY_1 = 0, + + /* Rx serial clock div by 2 */ + CS4224_CLKDIV_DDIV_BY_2 = 1, + + /* Rx serial clock div by 4 */ + CS4224_CLKDIV_DDIV_BY_4 = 2, + + /* Rx serial clock div by 8 */ + CS4224_CLKDIV_DDIV_BY_8 = 3, + + /* Rx serial clock div by 16 */ + CS4224_CLKDIV_DDIV_BY_16 = 4, + + /* Rx serial clock div by 32 */ + CS4224_CLKDIV_DDIV_BY_32 = 5, + + /* Rx serial clock div by 64 */ + CS4224_CLKDIV_DDIV_BY_64 = 6, + + /* Rx serial clock div by 128 */ + CS4224_CLKDIV_DDIV_BY_128 = 7, + +}; + +/* Divider for the clock rate for receive data path */ +enum e_cs4224_ddiv_divide { + /* Divide by 1 */ + CS4224_DDIV_DIV1 = 0, + + /* Divide by 2 */ + CS4224_DDIV_DIV2 = 1, + + /* Divide by 4 */ + CS4224_DDIV_DIV4 = 2, + + /* Divide by 8 */ + CS4224_DDIV_DIV8 = 3, + + /* Divide by 16 */ + CS4224_DDIV_DIV16 = 4, + + /* Divide by 32 */ + CS4224_DDIV_DIV32 = 5, + + /* Divide by 64 */ + CS4224_DDIV_DIV64 = 6, + + /* Divide by 128 */ + CS4224_DDIV_DIV128 = 7 +}; + +/* The CLKDIV_CTRL, SRX_RDIV_SEL dividers + * NOTE: There are accidentally two structures like this, the other is below + */ +enum e_cs4224_clkdiv_rdiv_t { + /* Rx serial clock div by 8 */ + CS4224_CLKDIV_RDIV_BY_8 = 0, + + /* Rx serial clock div by 16 */ + CS4224_CLKDIV_RDIV_BY_16 = 1, + + /* Rx serial clock div by 32 */ + CS4224_CLKDIV_RDIV_BY_32 = 2, + + /* Rx serial clock div by 40 */ + CS4224_CLKDIV_RDIV_BY_40 = 3, + + /* Rx serial clock div by 64 */ + CS4224_CLKDIV_RDIV_BY_64 = 4, + + /* Rx serial clock div by 66 */ + CS4224_CLKDIV_RDIV_BY_66 = 5, + + /* Rx serial clock div by 80 */ + CS4224_CLKDIV_RDIV_BY_80 = 6, + + /* Rx serial clock div by 100 */ + CS4224_CLKDIV_RDIV_BY_100 = 7, + + /* Rx serial clock div by 128 */ + CS4224_CLKDIV_RDIV_BY_128 = 8, +}; + +/* The serial clock divider to receive PFD + * for comparison to the clock reference. + */ +enum e_cs4224_rdiv_divide { + /* Rx serial clock div by 8 */ + CS4224_RDIV_DIV8 = 0, + + /* Rx serial clock div by 16 */ + CS4224_RDIV_DIV16 = 1, + + /* Rx serial clock div by 32 */ + CS4224_RDIV_DIV32 = 2, + + /* Rx serial clock div by 40 */ + CS4224_RDIV_DIV40 = 3, + + /* Rx serial clock div by 64 */ + CS4224_RDIV_DIV64 = 4, + + /* Rx serial clock div by 66 */ + CS4224_RDIV_DIV66 = 5, + + /* Rx serial clock div by 80 */ + CS4224_RDIV_DIV80 = 6, + + /* Rx serial clock div by 100 */ + CS4224_RDIV_DIV100 = 7, + + /* Rx serial clock div by 128 */ + CS4224_RDIV_DIV128 = 8, +}; + +/* Accumulator width options for the Fractional-N divider */ +enum e_cs4224_fracdiv_accumulator_width { + /* 8 bit accumulator */ + CS4224_FRACDIV_ACCUM_WIDTH_8BIT = 0, + + /* 16 bit accumulator */ + CS4224_FRACDIV_ACCUM_WIDTH_16BIT = 1, + + /* 24 bit accumulator */ + CS4224_FRACDIV_ACCUM_WIDTH_24BIT = 2, + + /* 32 bit accumulator */ + CS4224_FRACDIV_ACCUM_WIDTH_32BIT = 3, +}; + +/* The clock monitor clock source divider */ +enum e_cs4224_clk_mon_clksel_div { + /* Divide by 1 */ + CS4224_CLK_MON_DIV1 = 0, + + /* Divide by 4 */ + CS4224_CLK_MON_DIV4 = 1, + + /* Divide by 8 */ + CS4224_CLK_MON_DIV8 = 2, + + /* Divide by 16 */ + CS4224_CLK_MON_DIV16 = 3, +}; + +/* The per-port (pp) clock monitor clock source */ +enum e_cs4224_pp_clk_mon_clksel_src { + /* Clock source is SRX_CLK */ + CS4224_CLK_MON_PP_SRX = 0x00 << 2, + + /* Clock source is STX_CLK */ + CS4224_CLK_MON_PP_STX = 0x01 << 2, + + /* Clock source is SRX_CLK_LD */ + CS4224_CLK_MON_PP_CLK_LD = 0x02 << 2, + + /* Clock source is SRX_REF_LD */ + CS4224_CLK_MON_PP_REF_LD = 0x03 << 2, + + /* Clock source is SRX_FAST_CLK */ + CS4224_CLK_MON_PP_FAST = 0x04 << 2, + + /* Clock source is SRX_DIV32_OUT */ + CS4224_CLK_MON_PP_DIV32 = 0x05 << 2, + + /* Clock source is SRX_DIV80_OUT */ + CS4224_CLK_MON_PP_DIV80 = 0x06 << 2, + + /* Clock source is SRX_DIV64_OUT */ + CS4224_CLK_MON_PP_DIV64 = 0x07 << 2, + + /* Clock source is SRX_MON_CLK */ + CS4224_CLK_MON_PP_MON = 0x08 << 2, + + /* Clock source is no clock */ + CS4224_CLK_MON_PP_NO_CLK = 0x10 << 2, + + /* Clock source is reset dividers, output idle */ + CS4224_CLK_MON_PP_RESET = 0x3f, + +}; + +/* The global (gbl) clock monitor clock source */ +enum e_cs4224_gbl_clk_mon_clksel_src { + /* Clock source is process monitor */ + CS4224_CLK_MON_GBL_PMON = 0x00 << 2, + + /* Clock source is process monitor divided by 2 */ + CS4224_CLK_MON_GBL_PMOND2 = 0x01 << 2, + + /* Clock source is process monitor divided by 4 */ + CS4224_CLK_MON_GBL_PMOND4 = 0x02 << 2, + + /* Clock source is reference clock */ + CS4224_CLK_MON_GBL_REFCLK = 0x03 << 2, + + /* Clock source is clockless VCO clock */ + CS4224_CLK_MON_GBL_VCO = 0x04 << 2, + + /* Clock source is GPIO1 */ + CS4224_CLK_MON_GBL_GPIO1 = 0x06 << 2, + + /* Clock source is GPIO2 */ + CS4224_CLK_MON_GBL_GPIO2 = 0x07 << 2, + + /* Clock source is port pair 0 egress selected clock */ + CS4224_CLK_MON_GBL_PP0EGR = 0x08 << 2, + + /* Clock source is port pair 0 ingress selected clock */ + CS4224_CLK_MON_GBL_PP0ING = 0x09 << 2, + + /* Clock source is port pair 1 egress selected clock */ + CS4224_CLK_MON_GBL_PP1EGR = 0x0a << 2, + + /* Clock source is port pair 1 ingress selected clock */ + CS4224_CLK_MON_GBL_PP1ING = 0x0b << 2, + + /* Clock source is port pair 2 egress selected clock */ + CS4224_CLK_MON_GBL_PP2EGR = 0x0c << 2, + + /* Clock source is port pair 2 ingress selected clock */ + CS4224_CLK_MON_GBL_PP2ING = 0x0d << 2, + + /* Clock source is port pair 3 egress selected clock */ + CS4224_CLK_MON_GBL_PP3EGR = 0x0e << 2, + + /* Clock source is port pair 3 ingress selected clock */ + CS4224_CLK_MON_GBL_PP3ING = 0x0f << 2, + + /* Clock source is no clock */ + CS4224_CLK_MON_GBL_NO_CLK = 0x10 << 2, + + /* Clock source is reset dividers, output idle */ + CS4224_CLK_MON_GBL_RESET = 0x7f, +}; + +/* Used to select the driver being configured */ +enum e_cs4224_tx_driver_interface { + /* The host side transmitter */ + CS4224_TX_HOST_INTERFACE = 0, + + /* The line side transmitter */ + CS4224_TX_LINE_INTERFACE = 1, + + /* If in simplex mode this automatically + * determines the appropriate transmitter for the channel + */ + CS4224_TX_SIMPLEX_INTERFACE = 2, +}; + +/* PCS Monitor Status */ +struct cs4224_pcs_monitor_status_t { + /* PCS monitor reveiver state machine sync status */ + unsigned char sync; + + /* PCS monitor is in a high bit error state (XGPCS only) */ + unsigned int high_ber; +}; + +/* FEC Statistics */ +struct cs4224_fec_stats_t { + /* Number of FEC blocks transmitted by the line side Tx module */ + unsigned int tx_blk_total; + + /* Number of FEC blocks received (decoded) by the line side Rx module */ + unsigned int rx_blk_total; + + /* Number of FEC blocks successfully corrected by the Rx module */ + unsigned int rx_blk_corr; + + /* Number of FEC blocks unable to be corrected by the Rx module */ + unsigned int rx_blk_uncorr; + + /* Number of zero bit errors detected by the Rx module */ + unsigned int rx_zero_errs; + + /* Number of one bit errors detected by the Rx module */ + unsigned int rx_one_errs; +}; + +/* + * Configuration for the per-port (pp) clock monitor + * Use cs4224_pp_clk_mon_cfg_init() to initialize + */ +struct cs4224_pp_clk_mon_cfg_t { + /* Select the clock source divider */ + enum e_cs4224_clk_mon_clksel_div clksel_divider; + + /* Select the clock source */ + enum e_cs4224_pp_clk_mon_clksel_src clksel_src; + + /* Start counting flag */ + unsigned char go; + + /* Enable counter to free run */ + unsigned char free_run; + + /* Time duration to count */ + unsigned short duration; + + /* minimum count threshold */ + unsigned int min_thresh; + + /* maximum count threshold */ + unsigned int max_thresh; +}; + +/* Configuration for the global (gbl) clock monitor */ +struct cs4224_gbl_clk_mon_cfg_t { + /* Select the clock source divider */ + enum e_cs4224_clk_mon_clksel_div clksel_divider; + + /* Select the clock source */ + enum e_cs4224_gbl_clk_mon_clksel_src clksel_src; + + /* Start counting flag */ + unsigned char go; + + /* Enable counter to free run */ + unsigned char free_run; + + /* Time duration to count */ + unsigned short duration; + + /* minimum count threshold, 32 bits */ + unsigned short min_thresh_0; + unsigned short min_thresh_1; + + /* maximum count threshold, 32 bits */ + unsigned short max_thresh_0; + unsigned short max_thresh_1; +}; + +/* + * This structure is used to store state information + * that is used when enabling a 2x2 or broadcast + * switch. + */ +struct cs4224_switch_state_t { + /* The state of the line SRX0_RX_CLKOUT_CTRL register */ + unsigned short line_srx0_rx_clkout_ctrl; + + /* The state of the host SRX0_RX_CLKOUT_CTRL register */ + unsigned short host_srx0_rx_clkout_ctrl; + + /* The state of the line COMMON_STX0_MISC register */ + unsigned short line_stx0_misc; + + /* The state of the host COMMON_STX0_MISC register */ + unsigned short host_stx0_misc; + + /* The state of the line DSP_MSEQ_POWER_DOWN_LSB register */ + unsigned short line_mseq_power_down; + + /* The state of the host DSP_MSEQ_POWER_DOWN_LSB register */ + unsigned short host_mseq_power_down; + + /* The state of the line STX0_DRIVER_CONFIG register */ + unsigned short line_stx0_driver_config; + + /* The state of the host STX0_DRIVER_CONFIG register */ + unsigned short host_stx0_driver_config; + + /* The state of the line DSP_MSEQ_MAIL_SEL register */ + unsigned short line_dsp_mseq_mail_sel; + + /* The state of the host DSP_MSEQ_MAIL_SEL register */ + unsigned short host_dsp_mseq_mail_sel; + + /* The state of the host SRX0_VCO_CONFIG register */ + unsigned short host_srx0_vco_config; + + /* The state of the host SRX0_AGC_CONFIG1 register */ + unsigned short host_srx0_agc_config1; + + /* The state of the host SRX0_DFE_CONFIG register */ + unsigned short host_srx0_dfe_config; + + /* The state of the line SRX0_RX_CONFIG register */ + unsigned short line_srx0_rx_config; + + /* The state of the host SRX0_RX_CONFIG register */ + unsigned short host_srx0_rx_config; + + /* The state of the line MSEQ_SPARE12_LSB register */ + unsigned short line_spare12_lsb; + + /* The state of the host MSEQ_SPARE12_LSB register */ + unsigned short host_spare12_lsb; + + /* The state of the line MSEQ_SPARE26_LSB register */ + unsigned short line_spare26_lsb; +}; + +/* + * This structure is used to maintain device state when + * managing the duplex 2x2 protection switching. It must + * be initialized when the switch is first initialized and + * then gets passed to consecutive API calls to manage + * the h/w state. + */ +struct cs4224_switch_pair_state_t { + /* + * This flag is used to determine whether or not the + * switch state has been initialized. Before activating the + * switch for the first time this variable should be set to + * FALSE to ensure that the API knows that the state + * should be stored. + */ + unsigned char initialized; + + /* + * This flag is managed by the user to setup the switch in low + * latency mode. This bypasses the digital path through + * the chip and achieves the lowest possible latency. However + * it cannot be used when KR-AN or FC-AN are enabled + */ + unsigned char low_latency_switching; + + /* + * State space used to manage the two slices of + * the switch pair. This is managed automatically + * by the API. + */ + struct cs4224_switch_state_t slices[2]; + + /* + * For duplex switching on dual-die devices, write the switch config to + * both dies at the same time. + * + * Ignored for simplex switching. Only supported in superfast methods. + * Only relevant for the 8-port duplex devices. + * + * For which pairs will be set at the same time: + * + * @{table, + * -h Slice pairs that will be set when broadcast is enabled + * -s Die 1 ! Die 0 + * - 0/1 ! 6/7 + * - 2/3 ! 4/5 + * } + */ + unsigned char broadcast; +}; + +/* Configuration for the SyncE application */ +struct cs4224_rules_synce_config_t { + /* Enable SyncE */ + unsigned char enable; + + /* The core fracN integer divisor */ + unsigned short divisor; + + /* The core fracN numerator */ + unsigned int numerator; + + /* The clock divider */ + enum e_cs4224_clk_mon_clksel_div clk_divider; + + /* the GPIO to ouput the SyncE signal, + * range GPIO1 thru GPIO4 and GPIO_INTERR + */ + unsigned char gpio; + + /* the direction, line Rx or host Rx */ + enum e_cs4224_datapath_dir_t dir; +}; + +/* Configuration for the CDR frac-N's in the Rx and Tx interfaces */ +struct cs4224_rules_fracdiv_config_t { + /* Enable the fracN block */ + unsigned char enable; + + /* The integer divisor, 8 bits wide */ + unsigned short divisor; + + /* The numerator, 24bits wide */ + unsigned int numerator; + +}; + +/* Configuration rules for trace loss on the Rx or Tx interfaces */ +struct cs4224_rules_intf_t { + /* Trace loss setting */ + enum e_cs4224_trace_loss traceloss; +}; + +struct cs4224_advanced_rules_t { + unsigned char phsel_bypass; + unsigned short phsel_bypass_value; +}; + +/* Rx interface rules for device initialization */ +struct cs4224_rules_rx_if_t { + /* The EDC mode for the Rx interface (simplex only) */ + enum e_cs4224_edc_mode splx_edc_mode; + + /* The line EDC mode for the Rx interface (duplex only) */ + enum e_cs4224_edc_mode dplx_line_edc_mode; + + /* The host EDC mode for the Rx interface (duplex only) */ + enum e_cs4224_edc_mode dplx_host_edc_mode; + + /* Rx equalization rules (simplex only) */ + struct cs4224_rules_intf_t splx_eq; + + /* Rx line equalization rules (duplex only) */ + struct cs4224_rules_intf_t dplx_line_eq; + + /* Rx host equalization rules (duplex only) */ + struct cs4224_rules_intf_t dplx_host_eq; +}; + +/* Tx interface rules for device initialization */ +struct cs4224_rules_tx_if_t { + /* Disable the transmitter (simplex only) */ + unsigned char splx_disable; + + /* Disable the line transmitter (duplex only) */ + unsigned char dplx_line_disable; + + /* Disable the host transmitter (duplex only) */ + unsigned char dplx_host_disable; + + /* Tx driver initialization rules (simplex only) */ + struct cs4224_rules_intf_t splx_driver; + + /* Tx line driver initialization rules (duplex only) */ + struct cs4224_rules_intf_t dplx_line_driver; + + /* Tx host driver initialization rules (duplex only) */ + struct cs4224_rules_intf_t dplx_host_driver; + + /* power-down flag */ + unsigned char power_down; +}; + +/* Divider values for controlling CLKDIV_CTRL register */ +struct cs4224_rules_div_config_t { + /* Enable the manual CLKDIV_CTRL register updates */ + unsigned char enable; + + /* The SRX_RDIV_SEL divider */ + unsigned short rdiv; + + /* The SRX_DDIV_SEL divider */ + unsigned short ddiv; + + /* The SRX_FASTDIV_SEL divider */ + unsigned short fastdiv; +}; + +/* + * This structure is used to manage callback functions + * required during the initialization process. + */ +struct cs4224_callback_t { + /* Pointer to user data passed back to the callback */ + void *user_data; + + /* Pointer to the callback method */ + void *fcn_ptr; +}; + +/* KR-AN specific rules */ +struct cs4224_rules_kran_t { + /* The advertised supported datarates, + * see enum e_cs4224_kran_data_rates_t + */ + unsigned int data_rates; + + /* FEC ability flag (F0) */ + unsigned char fec_ability_f0; + + /* FEC requested flag (F1) */ + unsigned char fec_requested_f1; + + /* Pause ability flag (C0) */ + unsigned char pause_ability_c0; + + /* Pause ability flag (C1) */ + unsigned char pause_ability_c1; + + /* Remote Fault flag (D13) */ + unsigned char remote_fault_d13; + + /* Training enable flag */ + unsigned char allow_training; + + unsigned char wait_for_an_done; + + /* A callback method */ + struct cs4224_callback_t poll_kran_callback; + + /* Internal advanced settings */ + struct cs4224_kran_advanced_config_t_s advanced; +}; + +enum e_cs4224_fcan_data_rate_t { + /* 1 GE */ + CS4224_FCAN_DATA_RATE_1G = 0x1, + + /* 2 GE */ + CS4224_FCAN_DATA_RATE_2G = 0X2, + + /* 4 GE */ + CS4224_FCAN_DATA_RATE_4G = 0x4, + + /* 8 GE */ + CS4224_FCAN_DATA_RATE_8G = 0x8, + + /* 16 GE */ + CS4224_FCAN_DATA_RATE_16G = 0x10, + + /* Disabled - the default value for the negotiated_rate + * variable to prevent compilation problems + */ + CS4224_FCAN_DATA_RATE_DISABLED = 0, +}; + +enum e_cs4224_fcan_an_status_t { + /* FC-AN negotiated a data rate */ + CS4224_FCAN_AN_DONE = 0x1, + + /* FC-AN could not negotiate a data rate */ + CS4224_FCAN_AN_NOT_DONE = 0x2, +}; + +/* FC-AN VCO mode */ +enum e_cs4224_fcan_vco_mode_t { + /* VCO in PD mode (through-timing) */ + CS4224_FCAN_VCO_PD_MODE = 0, + + /* VCO in PFD mode (local-timing) */ + CS4224_FCAN_VCO_PFD_MODE, +}; + +/* FC-AN advanced rules for debugging */ +struct cs4224_fcan_advanced_t { + /* Set Main tap to Maximum */ + unsigned char enable_tp_main_tap_to_max; + + /* Turn on adaptive post */ + unsigned char enable_tp_adaptive_post; + + /* Send Preset at the begining of training */ + unsigned char enable_tp_send_preset; + + /* Send Init at the begining of training */ + unsigned char enable_tp_send_init; + + /* Force local_rx_ready initial condition */ + unsigned char enable_tp_frc_lcl_rx_ready; + + /* lp_status inital condition */ + unsigned char enable_tp_lp_status; + + /* Send hold inital condition */ + unsigned char enable_tp_send_hold; + + /* SWC in limits initial condition */ + unsigned char enable_tp_swc_in_limits; + + /* Jump to cal.asm during train_taps if LOL */ + unsigned char enable_jmp_to_caldotasm; + + /* Disable FCAN power-savings */ + unsigned char disable_fc_power_savings; + + /* When disabled, PCS sync not monitored on line side, testing only */ + unsigned char disable_pcs_checks; + + /* Enable training to work in the lab with no loss cables */ + unsigned char enable_no_loss; + + /* Start AN immediately after pre-AN config, default is TRUE */ + unsigned char start_an; +}; + +/* FC-AN specific rules */ +struct cs4224_rules_fcan_t { + unsigned short data_rates; + struct cs4224_callback_t poll_fcan_callback; + unsigned char wait_for_an_done; + enum e_cs4224_fcan_data_rate_t negotiated_rate; + unsigned char speed_negotiation_support; + unsigned char training_protocol_support; + unsigned char fec_capable; + unsigned char fec_request; + unsigned char transmitter_fixed; + struct cs4224_fcan_advanced_t advanced; +}; + +/* + * This structure defines the rules used to initialize the + * device. These rules serve as the high-level configuration + * switches that a user can adjust to control the behavior + * of the device(s). + */ +struct cs4224_rules_t { + enum e_cs4224_target_application application; + struct cs4224_rules_rx_if_t rx_if; + struct cs4224_rules_tx_if_t tx_if; + struct cs4224_rules_fcan_t fcan; + struct cs4224_rules_kran_t kran; + int ref_clk_rate; + struct cs4224_rules_div_config_t clkdiv; + struct cs4224_rules_fracdiv_config_t fracdiv; + struct cs4224_rules_synce_config_t synce; + unsigned char unsquelch_driver; + unsigned char tx_auto_squelch; + unsigned char enable_ac_decoupling_caps; + unsigned char show_debug_info; + unsigned char enable_power_savings; + unsigned char enable_fec; + enum e_cs4224_polarity_inv_t polarity_inv; + unsigned char enable_die_broadcast; + struct cs4224_advanced_rules_t advanced; + unsigned char mseq_dyn_reconfig; +}; + +/* VCO lock status */ +struct cs4224_vco_lock_status_t { + unsigned char rx_line_lock; + unsigned char rx_host_lock; +}; + +/* Struct to define a interface, used for methods that operate on multiple + * interfaces at a time (cs4224_wait_for_links_ready, etc) + */ +struct cs4224_interface_t { + unsigned int slice; + enum e_cs4224_mseq_id mseq_id; +}; + +typedef int(*cs4224_callback_lock)(unsigned int slice); +typedef int(*cs4224_callback_unlock)(unsigned int slice); + +/* Callback methods for implementing h/w locking */ +void cs4224_set_callback_for_lock(cs4224_callback_lock callback); +void cs4224_set_callback_for_unlock(cs4224_callback_unlock callback); + +void cs4224_reset_static_state(void); +void cs4224_reset_die_static_state(unsigned int die); + +unsigned int cs4224_get_die_from_slice( + unsigned int slice); + +int cs4224_reg_get_channel( + unsigned int slice, + unsigned int addr, + unsigned short *data); + +unsigned short cs4224_reg_read( + unsigned int slice, + unsigned int addr); + +int cs4224_reg_set_channel( + unsigned int channel, + unsigned int addr, + unsigned short data); + +int cs4224_reg_set_chk_channel( + unsigned int channel, + unsigned int addr, + unsigned short data); + +int cs4224_reg_get( + unsigned int die, + unsigned int addr, + unsigned short *data); + +int cs4224_reg_set( + unsigned int die, + unsigned int addr, + unsigned short data); + +int cs4224_lock( + unsigned int slice); + +int cs4224_unlock( + unsigned int slice); + +enum e_cs4224_hardware_id cs4224_hw_id( + unsigned int slice); + +unsigned char cs4224_is_hw_simplex(unsigned int slice); +unsigned char cs4224_is_hw_duplex(unsigned int slice); + +int cs4224_mon_volt_read_fixp( + unsigned int slice, + enum e_cs4224_mon_vlt_supply volt_source, + unsigned int *voltage); + +unsigned int cs4224_adj_pp( + unsigned int slice, + unsigned short addr); + +int cs4224_init_global_timer_fixp( + unsigned int slice, + unsigned int ref_clk_freq); + +unsigned int cs4224_adj_mseq( + unsigned int slice, + unsigned short addr); + +int cs4224_simplex_mate_slice( + unsigned int slice, + unsigned int *mate); + +unsigned char cs4224_line_rx_to_host_tx_dir( + unsigned int slice); + +int cs4224_version( + char *buffer, + unsigned int buffer_len); + +int cs4224_resync_elsto( + unsigned int slice, + unsigned short elsto_reg); + +int cs4224_init_vco( + unsigned int slice, + unsigned int addr); + +int cs4224_slice_change_rate_intf( + unsigned int slice, + enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules); + +int cs4224_rules_set_default( + enum e_cs4224_target_application application, + struct cs4224_rules_t *rules); + +int cs4224_slice_enter_operational_state( + unsigned int slice, + struct cs4224_rules_t *rules); + +int cs4224_get_mseq_id( + unsigned int slice, + enum e_cs4224_mseq_id *mseq_id); + +unsigned int cs4224_mseq_get_addr_offset( + unsigned int slice, + enum e_cs4224_mseq_id mseq); + +int cs4224_get_cfg_side( + unsigned int slice, + enum e_cs4224_cfg_sides_t *side); + +void cs4224_mseq_stall_set_delay(int us); +int cs4224_mseq_stall_get_delay(void); + +int cs4224_mseq_stall( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char stall); + +int cs4224_mseqs_stall( + struct cs4224_interface_t interfaces[], + unsigned short length, + unsigned char stall); + +int cs4224_mseq_enable_power_savings( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char enable); + +int cs4224_init_driver_settings( + unsigned int slice, + enum e_cs4224_tx_driver_interface intf, + unsigned short ctrla, + unsigned short ctrlb); + +int cs4224_config_polarity_inv_points( + unsigned int slice, + unsigned short inv_points); + +int cs4224_enable_polarity_inv( + unsigned int slice, + struct cs4224_rules_t *rules); + +int cs4224_query_polarity_inv( + unsigned int slice, + unsigned short *inv_points); + +int cs4224_debug_dump_polarity_inv( + unsigned int slice); + +void cs4224_pp_clk_mon_cfg_init( + struct cs4224_pp_clk_mon_cfg_t *clk_mon_cfg); + +int cs4224_pp_clock_monitor( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + struct cs4224_pp_clk_mon_cfg_t *clk_mon_cfg); + +int cs4224_pp_clock_monitor_freq_fixp( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + struct cs4224_pp_clk_mon_cfg_t *pp_clk_mon_cfg, + unsigned int ref_clk_rate, + unsigned short *freq); + +int cs4224_gbl_clock_monitor( + unsigned int slice, + struct cs4224_gbl_clk_mon_cfg_t *clk_mon_cfg); + +int cs4224_fracdiv_core_init( + unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned short divisor, + unsigned int numerator); + +int cs4224_fracdiv_cdr_init( + unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned short divisor, + unsigned int numerator); + +int cs4224_slice_soft_reset( + unsigned int slice); + +int cs4224_slice_soft_reset_intf( + unsigned int slice, + enum e_cs4224_cfg_sides_t intf); + +int cs4224_mseq_squelch_ctrl( + unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned char enable); + +int cs4224_send_squelch_request( + unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned char squelch); + +int cs4224_squelch_driver( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + unsigned char squelch); + +int cs4224_hard_reset_die(unsigned int die); +int cs4224_hard_reset(unsigned int slice); + +void cs4224_debug_ucode_show_version(unsigned int slice); + +int cs4224_mux_enable( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + unsigned char enable); + +int cs4224_demux_enable( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + unsigned char enable); + +int cs4224_init_edc_mode_set( + unsigned int slice, + struct cs4224_rules_t *rules); + +int cs4224_init_edc_mode_intf( + unsigned int slice, + struct cs4224_rules_t *rules, + enum e_cs4224_mseq_id intf); + +unsigned char cs4224_is_eeprom_finished(unsigned int die); + +int cs4224_wait_for_eeprom_finished( + unsigned int die, + unsigned int max_iterations, + unsigned int ms_delay_between_iterations); + +int cs4224_restore_powered_down_regs(unsigned int slice); + +int cs4224_slice_power_down( + unsigned int slice); + +int cs4224_save_edc_mode( + unsigned int slice, + unsigned short reg_offset, + enum e_cs4224_edc_mode edc_mode); + +int cs4224_query_edc_mode( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + enum e_cs4224_edc_mode *edc_mode); + +int cs4224_query_mseq_is_stalled( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char *stalled); + +int cs4224_query_mseq_power_savings( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char *enabled); + +const char *cs4224_translate_edc_mode(enum e_cs4224_edc_mode edc_mode); +const char *cs4224_translate_app_mode( + enum e_cs4224_target_application app_mode); +const char *cs4224_switch_translate_state( + enum e_cs4224_switch_action_t state); +const char *cs4224_translate_cfg_side(enum e_cs4224_cfg_sides_t side); +int cs4224_check_rules(unsigned int slice, struct cs4224_rules_t *rules); +unsigned int cs4224_query_data_rate(const struct cs4224_rules_t *rules); + +int cs4224_ucode_data_prgm_image( + unsigned int slice, + unsigned short microcode[], + unsigned int len_buffer); + +int cs4224_ucode_data_prgm_image_broadcast( + unsigned int slice, + unsigned short microcode[], + unsigned int len_buffer); + +void cs4223_glue_phydev_set(struct phy_device *phydev); + +#endif /* __CORTINA_API_H_ */ -- 2.17.1