From 28d25b88e3a2db575be4cc37ae7554ac00c1bfe1 Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Fri, 13 Aug 2021 12:13:02 +0200 Subject: [PATCH] =?utf8?q?arm64:=20dts:=20imx8mm-somdevices.dtsi:=20Set=20?= =?utf8?q?proper=20pins:=20=09=C2=B7=20Set=20proper=20pins=20to=20pmic,=20?= =?utf8?q?pcie,=20usdhc2,=20mipi=5Fcsi,=20sai5=20and=20uart2.=20=09=C2=B7?= =?utf8?q?=20Added=20SMARC=20gpios.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Josep Orga --- .../boot/dts/freescale/imx8mm-somdevices.dtsi | 57 ++++++++++++------- 1 file changed, 38 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi index 4ef4f33c6285..2aa4527a2df2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi @@ -188,8 +188,8 @@ reg = <0x25>; pinctrl-0 = <&pinctrl_pmic>; pinctrl-names = "default"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; regulators { buck1_reg: BUCK1 { @@ -357,8 +357,8 @@ &pcie0{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; - disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; - reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 27 GPIO_ACTIVE_LOW>; + wake-up-gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>, @@ -508,7 +508,8 @@ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; status = "okay"; @@ -554,10 +555,29 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + /* SOMDEVICES GPIOs */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 //GPIO00 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 //GPIO01 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 //GPIO02 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 //GPIO03 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 //GPIO04 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 //GPIO05 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 //GPIO06 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 //GPIO07 + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 //GPIO08 + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 //GPIO09 + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 //GPIO10 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 //GPIO11 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 //GPIO12 + >; + }; + pinctrl_csi: csi_grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 >; }; @@ -625,15 +645,15 @@ pinctrl_pcie0: pcie0grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x41 + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x41 >; }; pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x141 >; }; @@ -664,12 +684,10 @@ pinctrl_sai5: sai5grp { fsl,pins = < MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 - MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 - MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 - MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 >; }; @@ -685,8 +703,8 @@ pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 >; }; @@ -741,7 +759,8 @@ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x1c4 >; }; -- 2.17.1