From 28b3af555794826731fe81ba55455a3d1908efca Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 17 May 2017 02:08:19 -0500 Subject: [PATCH] MLK-14938-7 imx8: Add iomux driver Wrap the iomux settings through SCU APIs. Provide interfaces to follow other i.MX platforms. Users need to define the iomux_cfg_t which combines of three parts: | | can directly use the values in imx8qm_pins.h is optional if the select to use default mux. Otherwise using MUX_MODE_ALT(x) to set it. is the value for CONFIG, LP_CONFIG, PULL control, Drive Strength in Padring control register. Signed-off-by: Ye Li --- arch/arm/cpu/armv8/imx8/Makefile | 1 + arch/arm/cpu/armv8/imx8/iomux.c | 48 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-imx8/iomux.h | 42 ++++++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 arch/arm/cpu/armv8/imx8/iomux.c create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h diff --git a/arch/arm/cpu/armv8/imx8/Makefile b/arch/arm/cpu/armv8/imx8/Makefile index f60ee6ea9c..62ccac1fd3 100644 --- a/arch/arm/cpu/armv8/imx8/Makefile +++ b/arch/arm/cpu/armv8/imx8/Makefile @@ -8,3 +8,4 @@ obj-y += cpu.o obj-y += clock.o obj-y += fsl_mu_hal.o obj-y += fuse.o +obj-y += iomux.o diff --git a/arch/arm/cpu/armv8/imx8/iomux.c b/arch/arm/cpu/armv8/imx8/iomux.c new file mode 100644 index 0000000000..c6bd304402 --- /dev/null +++ b/arch/arm/cpu/armv8/imx8/iomux.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * configures a single pad in the iomuxer + */ +void imx8_iomux_setup_pad(iomux_cfg_t pad) +{ + sc_err_t err; + sc_ipc_t ipc; + + sc_pin_t pin_id = pad & PIN_ID_MASK; + + uint32_t val = (uint32_t)((pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT); + + ipc = gd->arch.ipc_channel_handle; + + val |= PADRING_IFMUX_EN_MASK; + val |= PADRING_GP_EN_MASK; + + err = sc_pad_set(ipc, pin_id, val); + if (err != SC_ERR_NONE) + printf("imx8_iomux sc_pad_set failed!, pin = %u, val = 0x%x\n", pin_id, val); + + debug("iomux: pin %d, val = 0x%x\n", pin_id, val); +} + +/* configures a list of pads within declared with IOMUX_PADS macro */ +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, + unsigned count) +{ + iomux_cfg_t const *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + imx8_iomux_setup_pad(*p); + p++; + } +} diff --git a/arch/arm/include/asm/arch-imx8/iomux.h b/arch/arm/include/asm/arch-imx8/iomux.h new file mode 100644 index 0000000000..b4e68af54b --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/iomux.h @@ -0,0 +1,42 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8_IOMUX_H__ +#define __ASM_ARCH_IMX8_IOMUX_H__ + +/* We use 64bits value for iomux settings. + * High 32bits are used for padring register value, + * low 16bits are used for pin index. + */ +typedef u64 iomux_cfg_t; + +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK (1 << 31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK (1 << 30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK (0x7 << 27) +#define PADRING_CONFIG_SHIFT 25 +#define PADRING_LPCONFIG_SHIFT 23 +#define PADRING_PULL_SHIFT 5 +#define PADRING_DSE_SHIFT 0 + + +#define MUX_PAD_CTRL_SHIFT 32 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT) +#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF) + +/* Valid mux alt0 to alt7 */ +#define MUX_MODE_ALT(x) (((iomux_cfg_t)x << MUX_MODE_SHIFT) & MUX_MODE_MASK) + + +void imx8_iomux_setup_pad(iomux_cfg_t pad); +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, + unsigned count); +#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */ -- 2.17.1