From 27d49179be1cdeff2ac85b2aede7e803e6264239 Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Tue, 4 Apr 2023 12:23:50 +0200 Subject: [PATCH] =?utf8?q?imx8mm-somdevices:=20arm64:=20dts:=20arm64:=20dt?= =?utf8?q?s:=20Change=20old=20I2C4=5FSCL=20pin.=20=C2=B7=20PMIC=20INT=20ch?= =?utf8?q?anged=20to=20SD1=5FSTROBE=5FGPIO2=5FIO11.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Josep Orga --- arch/arm/dts/imx8mm-somdevices.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mm-somdevices.dts b/arch/arm/dts/imx8mm-somdevices.dts index fce9d870e7..ba80aea4ae 100644 --- a/arch/arm/dts/imx8mm-somdevices.dts +++ b/arch/arm/dts/imx8mm-somdevices.dts @@ -158,7 +158,7 @@ compatible = "nxp,pca9450a"; /* PMIC PCA9450 PMIC_nINT GPIO5_I20 */ pinctrl-0 = <&pinctrl_pmic>; - gpio_intr = <&gpio5 20 GPIO_ACTIVE_LOW>; + gpio_intr = <&gpio2 11 GPIO_ACTIVE_LOW>; regulators { #address-cells = <1>; @@ -455,7 +455,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x141 + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x141 >; }; -- 2.17.1