From 21cb81b4f0bc3991929f4735efb4e07269405985 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Thu, 7 Mar 2019 16:22:26 +0200 Subject: [PATCH] MLK-21084 arm64: dts: Copy all imx8 dts Copy all from rel_imx_4.14.98_2.0.0_ga_rc1 in order to help external build systems. Signed-off-by: Leonard Crestez --- arch/arm64/boot/dts/freescale/Makefile | 118 +- .../dts/freescale/fsl-imx8dm-lpddr4-arm2.dts | 109 ++ arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi | 42 + .../dts/freescale/fsl-imx8dx-17x17-val.dts | 26 + .../dts/freescale/fsl-imx8dx-lpddr4-arm2.dts | 26 + .../dts/freescale/fsl-imx8dxp-lpddr4-arm2.dts | 35 + .../dts/freescale/fsl-imx8mm-ddr3l-val.dts | 418 ++++++ .../freescale/fsl-imx8mm-ddr4-evk-rm67191.dts | 49 + .../dts/freescale/fsl-imx8mm-ddr4-evk.dts | 113 ++ .../freescale/fsl-imx8mm-ddr4-qca9377-evk.dts | 33 + .../dts/freescale/fsl-imx8mm-ddr4-val.dts | 541 +++++++ .../dts/freescale/fsl-imx8mm-evk-ak4497.dts | 78 + .../dts/freescale/fsl-imx8mm-evk-ak5558.dts | 32 + .../freescale/fsl-imx8mm-evk-audio-tdm.dts | 25 + .../boot/dts/freescale/fsl-imx8mm-evk-m4.dts | 85 ++ .../freescale/fsl-imx8mm-evk-revb-rm67191.dts | 49 + .../dts/freescale/fsl-imx8mm-evk-revb.dts | 32 + .../dts/freescale/fsl-imx8mm-evk-rm67191.dts | 35 + .../dts/freescale/fsl-imx8mm-evk-root.dts | 65 + .../dts/freescale/fsl-imx8mq-ddr3l-arm2.dts | 371 +++++ .../fsl-imx8mq-ddr4-arm2-gpmi-nand.dts | 52 + .../dts/freescale/fsl-imx8mq-ddr4-arm2.dts | 363 +++++ .../dts/freescale/fsl-imx8mq-evk-ak4497.dts | 95 ++ .../freescale/fsl-imx8mq-evk-audio-tdm.dts | 25 + .../boot/dts/freescale/fsl-imx8mq-evk-b3.dts | 99 ++ .../fsl-imx8mq-evk-dcss-adv7535-b3.dts | 16 + .../freescale/fsl-imx8mq-evk-dcss-adv7535.dts | 16 + .../fsl-imx8mq-evk-dcss-adv7535.dtsi | 79 + .../fsl-imx8mq-evk-dcss-rm67191-b3.dts | 16 + .../freescale/fsl-imx8mq-evk-dcss-rm67191.dts | 16 + .../fsl-imx8mq-evk-dcss-rm67191.dtsi | 131 ++ .../boot/dts/freescale/fsl-imx8mq-evk-dp.dts | 26 + .../boot/dts/freescale/fsl-imx8mq-evk-drm.dts | 41 + .../fsl-imx8mq-evk-dual-display-b3.dts | 42 + .../freescale/fsl-imx8mq-evk-dual-display.dts | 42 + .../boot/dts/freescale/fsl-imx8mq-evk-edp.dts | 25 + .../dts/freescale/fsl-imx8mq-evk-inmate.dts | 207 +++ .../fsl-imx8mq-evk-lcdif-adv7535-b3.dts | 16 + .../fsl-imx8mq-evk-lcdif-adv7535.dts | 16 + .../fsl-imx8mq-evk-lcdif-adv7535.dtsi | 71 + .../fsl-imx8mq-evk-lcdif-rm67191-b3.dts | 16 + .../fsl-imx8mq-evk-lcdif-rm67191.dts | 16 + .../fsl-imx8mq-evk-lcdif-rm67191.dtsi | 101 ++ .../boot/dts/freescale/fsl-imx8mq-evk-m4.dts | 63 + .../freescale/fsl-imx8mq-evk-mipi-csi2.dts | 38 + .../dts/freescale/fsl-imx8mq-evk-pcie1-m2.dts | 82 ++ .../boot/dts/freescale/fsl-imx8mq-evk-pdm.dts | 46 + .../dts/freescale/fsl-imx8mq-evk-root.dts | 110 ++ .../freescale/fsl-imx8qm-ddr4-arm2-hdmi.dts | 103 ++ .../dts/freescale/fsl-imx8qm-ddr4-arm2.dts | 1300 +++++++++++++++++ .../freescale/fsl-imx8qm-enet2-tja1100.dtsi | 72 + .../freescale/fsl-imx8qm-lpddr4-arm2-8cam.dts | 45 + .../freescale/fsl-imx8qm-lpddr4-arm2-dom0.dts | 331 +++++ .../freescale/fsl-imx8qm-lpddr4-arm2-domu.dts | 630 ++++++++ .../fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts | 46 + .../freescale/fsl-imx8qm-lpddr4-arm2-dp.dts | 60 + .../fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts | 65 + .../fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dts | 16 + .../fsl-imx8qm-lpddr4-arm2-hdmi-in.dts | 70 + .../freescale/fsl-imx8qm-lpddr4-arm2-hdmi.dts | 107 ++ .../freescale/fsl-imx8qm-lpddr4-arm2-hsic.dts | 75 + ...imx8qm-lpddr4-arm2-it6263-dual-channel.dts | 35 + ...x8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dts | 71 + .../fsl-imx8qm-lpddr4-arm2-lpspi-slave.dts | 32 + .../fsl-imx8qm-lpddr4-arm2-lpspi.dts | 79 + .../freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts | 198 +++ .../fsl-imx8qm-lpddr4-arm2-spdif.dts | 205 +++ .../freescale/fsl-imx8qm-lpddr4-arm2-usb3.dts | 113 ++ .../freescale/fsl-imx8qm-lpddr4-arm2_ca53.dts | 24 + .../freescale/fsl-imx8qm-lpddr4-arm2_ca72.dts | 32 + .../freescale/fsl-imx8qm-mek-dom0-dpu2.dts | 784 ++++++++++ .../dts/freescale/fsl-imx8qm-mek-dom0.dts | 917 ++++++++++++ .../dts/freescale/fsl-imx8qm-mek-domu-car.dts | 155 ++ .../fsl-imx8qm-mek-domu-dpu1-hdmi.dts | 43 + .../freescale/fsl-imx8qm-mek-domu-dpu1.dts | 991 +++++++++++++ .../freescale/fsl-imx8qm-mek-domu-hdmi.dts | 98 ++ .../dts/freescale/fsl-imx8qm-mek-domu.dts | 1241 ++++++++++++++++ .../freescale/fsl-imx8qm-mek-dsi-rm67191.dts | 65 + .../boot/dts/freescale/fsl-imx8qm-mek-dsp.dts | 198 +++ .../fsl-imx8qm-mek-enet2-tja1100.dts | 16 + .../dts/freescale/fsl-imx8qm-mek-hdmi-in.dts | 67 + .../dts/freescale/fsl-imx8qm-mek-hdmi.dts | 88 ++ .../dts/freescale/fsl-imx8qm-mek-inmate.dts | 287 ++++ .../fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dts | 71 + .../dts/freescale/fsl-imx8qm-mek-ov5640.dts | 153 ++ .../dts/freescale/fsl-imx8qm-mek-root.dts | 119 ++ .../dts/freescale/fsl-imx8qm-mek-rpmsg.dts | 17 + .../dts/freescale/fsl-imx8qm-mek-rpmsg.dtsi | 93 ++ .../dts/freescale/fsl-imx8qm-mek_ca53.dts | 23 + .../dts/freescale/fsl-imx8qm-mek_ca72.dts | 31 + .../boot/dts/freescale/fsl-imx8qm-xen.dtsi | 576 ++++++++ .../dts/freescale/fsl-imx8qp-lpddr4-arm2.dts | 25 + arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi | 43 + .../dts/freescale/fsl-imx8qxp-17x17-val.dts | 26 + .../dts/freescale/fsl-imx8qxp-ddr3l-val.dts | 30 + .../freescale/fsl-imx8qxp-enet2-tja1100.dtsi | 59 + .../freescale/fsl-imx8qxp-lpddr4-arm2-a0.dts | 24 + .../fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dts | 61 + .../freescale/fsl-imx8qxp-lpddr4-arm2-dsp.dts | 112 ++ .../fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dts | 16 + .../fsl-imx8qxp-lpddr4-arm2-enet2.dts | 27 + .../fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts | 67 + .../fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts | 21 + .../fsl-imx8qxp-lpddr4-arm2-lpspi.dts | 78 + .../freescale/fsl-imx8qxp-lpddr4-arm2-mlb.dts | 23 + .../freescale/fsl-imx8qxp-lpddr4-arm2-mqs.dts | 60 + .../fsl-imx8qxp-lpddr4-arm2-spdif.dts | 59 + .../fsl-imx8qxp-lpddr4-arm2-wm8962.dts | 113 ++ .../boot/dts/freescale/fsl-imx8qxp-mek-a0.dts | 23 + .../dts/freescale/fsl-imx8qxp-mek-dom0.dts | 90 ++ .../freescale/fsl-imx8qxp-mek-dsi-rm67191.dts | 63 + .../dts/freescale/fsl-imx8qxp-mek-dsp.dts | 171 +++ .../fsl-imx8qxp-mek-enet2-tja1100.dts | 16 + .../dts/freescale/fsl-imx8qxp-mek-enet2.dts | 27 + .../dts/freescale/fsl-imx8qxp-mek-inmate.dts | 294 ++++ ...-imx8qxp-mek-it6263-lvds0-dual-channel.dts | 30 + ...-imx8qxp-mek-it6263-lvds1-dual-channel.dts | 30 + .../fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dts | 50 + .../fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dts | 50 + .../dts/freescale/fsl-imx8qxp-mek-lcdif.dts | 97 ++ .../fsl-imx8qxp-mek-lvds0-it6263.dtsi | 58 + .../fsl-imx8qxp-mek-lvds1-it6263.dtsi | 58 + .../fsl-imx8qxp-mek-ov5640-rpmsg.dts | 24 + .../dts/freescale/fsl-imx8qxp-mek-ov5640.dts | 24 + .../dts/freescale/fsl-imx8qxp-mek-ov5640.dtsi | 126 ++ .../dts/freescale/fsl-imx8qxp-mek-root.dts | 111 ++ .../dts/freescale/fsl-imx8qxp-mek-rpmsg.dts | 17 + .../dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi | 200 +++ .../boot/dts/freescale/fsl-imx8qxp-xen.dtsi | 61 + .../dts/freescale/fsl-imx8x-17x17-val.dtsi | 155 ++ 130 files changed, 16505 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8dx-17x17-val.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8dx-lpddr4-arm2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8dxp-lpddr4-arm2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr3l-val.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-qca9377-evk.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-val.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak4497.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak5558.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-audio-tdm.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-m4.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-revb-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-revb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-root.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-audio-tdm.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535-b3.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191-b3.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dp.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display-b3.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-edp.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-inmate.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535-b3.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191-b3.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-mipi-csi2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pcie1-m2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2-hdmi.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-enet2-tja1100.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-8cam.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dom0.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi-in.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hsic.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi-slave.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-usb3.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca53.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca72.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0-dpu2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-car.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1-hdmi.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-hdmi.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsi-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsp.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-enet2-tja1100.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi-in.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-ov5640.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-rpmsg.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-rpmsg.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca53.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca72.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-17x17-val.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-ddr3l-val.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-a0.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsp.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mlb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mqs.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-spdif.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts create mode 100755 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-a0.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dom0.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsi-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsp.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2-tja1100.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-inmate.dts create mode 100755 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dts create mode 100755 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lcdif.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds0-it6263.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds1-it6263.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640-rpmsg.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-root.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dts create mode 100755 arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qxp-xen.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8x-17x17-val.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 1edde30997e5..195649ba738f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -15,8 +15,118 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ - fsl-imx8qm-mek.dtb + fsl-imx8qm-lpddr4-arm2-dom0.dtb \ + fsl-imx8qm-lpddr4-arm2-domu.dtb \ + fsl-imx8qm-ddr4-arm2.dtb \ + fsl-imx8qm-ddr4-arm2-hdmi.dtb \ + fsl-imx8qm-lpddr4-arm2_ca53.dtb \ + fsl-imx8qm-lpddr4-arm2_ca72.dtb \ + fsl-imx8qm-mek.dtb \ + fsl-imx8qm-mek-rpmsg.dtb \ + fsl-imx8qm-mek-dsp.dtb \ + fsl-imx8qm-mek-ov5640.dtb \ + fsl-imx8qm-mek_ca53.dtb \ + fsl-imx8qm-mek_ca72.dtb \ + fsl-imx8qm-mek-hdmi.dtb \ + fsl-imx8qm-mek-hdmi-in.dtb \ + fsl-imx8qm-mek-dsi-rm67191.dtb \ + fsl-imx8qm-mek-enet2-tja1100.dtb \ + fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ + fsl-imx8qm-mek-dom0.dtb \ + fsl-imx8qm-mek-dom0-dpu2.dtb \ + fsl-imx8qm-mek-domu.dtb \ + fsl-imx8qm-mek-domu-car.dtb \ + fsl-imx8qm-mek-domu-dpu1.dtb \ + fsl-imx8qm-mek-domu-dpu1-hdmi.dtb \ + fsl-imx8qm-mek-root.dtb \ + fsl-imx8qm-mek-inmate.dtb \ + fsl-imx8qm-lpddr4-arm2-dp.dtb \ + fsl-imx8qm-lpddr4-arm2-hdmi.dtb \ + fsl-imx8qm-lpddr4-arm2-hdmi-in.dtb \ + fsl-imx8qm-lpddr4-arm2-8cam.dtb \ + fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dtb \ + fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dtb \ + fsl-imx8qm-lpddr4-arm2-lpspi.dtb \ + fsl-imx8qm-lpddr4-arm2-lpspi-slave.dtb \ + fsl-imx8qm-lpddr4-arm2-spdif.dtb \ + fsl-imx8qm-lpddr4-arm2-mqs.dtb \ + fsl-imx8qm-lpddr4-arm2-usb3.dtb \ + fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dtb \ + fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dtb \ + fsl-imx8qm-lpddr4-arm2-hsic.dtb \ + fsl-imx8dm-lpddr4-arm2.dtb \ + fsl-imx8qp-lpddr4-arm2.dtb \ + fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dtb dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ - fsl-imx8qxp-mek.dtb -dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-evk.dtb -dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-evk.dtb + fsl-imx8qxp-mek.dtb \ + fsl-imx8qxp-mek-rpmsg.dtb \ + fsl-imx8qxp-mek-dsp.dtb \ + fsl-imx8qxp-mek-dom0.dtb \ + fsl-imx8qxp-mek-ov5640.dtb \ + fsl-imx8qxp-mek-ov5640-rpmsg.dtb \ + fsl-imx8qxp-mek-enet2.dtb \ + fsl-imx8qxp-mek-enet2-tja1100.dtb \ + fsl-imx8qxp-mek-dsi-rm67191.dtb \ + fsl-imx8qxp-mek-a0.dtb \ + fsl-imx8qxp-mek-lcdif.dtb \ + fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dtb \ + fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dtb \ + fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \ + fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dtb \ + fsl-imx8qxp-mek-root.dtb \ + fsl-imx8qxp-mek-inmate.dtb \ + fsl-imx8qxp-lpddr4-arm2-enet2.dtb \ + fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dtb \ + fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dtb \ + fsl-imx8qxp-lpddr4-arm2-lpspi.dtb \ + fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dtb \ + fsl-imx8qxp-lpddr4-arm2-spdif.dtb \ + fsl-imx8qxp-lpddr4-arm2-mlb.dtb \ + fsl-imx8qxp-lpddr4-arm2-mqs.dtb \ + fsl-imx8qxp-lpddr4-arm2-wm8962.dtb \ + fsl-imx8qxp-lpddr4-arm2-dsp.dtb \ + fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dtb \ + fsl-imx8qxp-lpddr4-arm2-a0.dtb \ + fsl-imx8qxp-17x17-val.dtb \ + fsl-imx8qxp-ddr3l-val.dtb \ + fsl-imx8dx-17x17-val.dtb \ + fsl-imx8dx-lpddr4-arm2.dtb \ + fsl-imx8dxp-lpddr4-arm2.dtb +dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \ + fsl-imx8mq-ddr4-arm2.dtb \ + fsl-imx8mq-ddr4-arm2-gpmi-nand.dtb \ + fsl-imx8mq-evk.dtb \ + fsl-imx8mq-evk-b3.dtb \ + fsl-imx8mq-evk-m4.dtb \ + fsl-imx8mq-evk-pcie1-m2.dtb \ + fsl-imx8mq-evk-lcdif-adv7535.dtb \ + fsl-imx8mq-evk-lcdif-adv7535-b3.dtb \ + fsl-imx8mq-evk-mipi-csi2.dtb \ + fsl-imx8mq-evk-pdm.dtb \ + fsl-imx8mq-evk-dcss-adv7535.dtb \ + fsl-imx8mq-evk-dcss-adv7535-b3.dtb \ + fsl-imx8mq-evk-dcss-rm67191.dtb \ + fsl-imx8mq-evk-dcss-rm67191-b3.dtb \ + fsl-imx8mq-evk-dual-display.dtb \ + fsl-imx8mq-evk-dual-display-b3.dtb \ + fsl-imx8mq-evk-ak4497.dtb \ + fsl-imx8mq-evk-audio-tdm.dtb \ + fsl-imx8mq-evk-drm.dtb \ + fsl-imx8mq-evk-root.dtb \ + fsl-imx8mq-evk-inmate.dtb \ + fsl-imx8mq-evk-dp.dtb \ + fsl-imx8mq-evk-edp.dtb +dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-evk.dtb \ + fsl-imx8mm-evk-ak4497.dtb \ + fsl-imx8mm-evk-m4.dtb \ + fsl-imx8mm-evk-ak5558.dtb \ + fsl-imx8mm-evk-audio-tdm.dtb \ + fsl-imx8mm-ddr3l-val.dtb \ + fsl-imx8mm-ddr4-evk.dtb \ + fsl-imx8mm-ddr4-val.dtb \ + fsl-imx8mm-evk-rm67191.dtb \ + fsl-imx8mm-evk-root.dtb \ + fsl-imx8mm-evk-revb.dtb \ + fsl-imx8mm-evk-revb-rm67191.dtb \ + fsl-imx8mm-ddr4-evk-rm67191.dtb \ + fsl-imx8mm-ddr4-qca9377-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts new file mode 100644 index 000000000000..412525fcf1b0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dm.dtsi" + +#include "fsl-imx8q-arm2.dtsi" + +/ { + model = "Freescale i.MX8DM ARM2"; + compatible = "fsl,imx8dm-arm2", "fsl,imx8dm", "fsl,imx8qm"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + +&mipi_dsi2 { + status = "disabled"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&display{ + ports = <&dpu1_disp0>, <&dpu1_disp1>; +}; + +&prg10 { + status = "disabled"; +}; + +&prg11 { + status = "disabled"; +}; + +&prg12 { + status = "disabled"; +}; + +&prg13 { + status = "disabled"; +}; + +&prg14 { + status = "disabled"; +}; + +&prg15 { + status = "disabled"; +}; + +&prg16 { + status = "disabled"; +}; + +&prg17 { + status = "disabled"; +}; + +&prg18 { + status = "disabled"; +}; + +&dpr3_channel1 { + status = "disabled"; +}; + +&dpr3_channel2 { + status = "disabled"; +}; + +&dpr3_channel3 { + status = "disabled"; +}; + +&dpr4_channel1 { + status = "disabled"; +}; + +&dpr4_channel2 { + status = "disabled"; +}; + +&dpr4_channel3 { + status = "disabled"; +}; + +&dpu2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi new file mode 100644 index 000000000000..eae337eb6422 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8DM"; + compatible = "fsl, imx8dm", "fsl,imx8qm"; + +}; + +&A53_0 { + device_type = ""; +}; + +&A53_1 { + device_type = ""; +}; + +&A53_2 { + device_type = ""; +}; + +&A53_3 { + device_type = ""; +}; + +&A53_L2 { + compatible = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-17x17-val.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-17x17-val.dts new file mode 100644 index 000000000000..f792ccb4e570 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-17x17-val.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dx.dtsi" + +#include "fsl-imx8x-17x17-val.dtsi" + +/ { + model = "Freescale i.MX8DX 17x17 Validation board"; + compatible = "fsl,imx8dx-17x17-val", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-lpddr4-arm2.dts new file mode 100644 index 000000000000..23d0714087f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-lpddr4-arm2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dx.dtsi" + +#include "fsl-imx8x-arm2.dtsi" + +/ { + model = "Freescale i.MX8DX ARM2"; + compatible = "fsl,imx8dx-arm2", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dxp-lpddr4-arm2.dts new file mode 100644 index 000000000000..c8b9e57f10d0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dxp-lpddr4-arm2.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dxp.dtsi" + +#include "fsl-imx8x-arm2.dtsi" + +/ { + model = "Freescale i.MX8DXP ARM2"; + compatible = "fsl,imx8dxp-arm2", "fsl,imx8dxp", "fsl,imx8qxp"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr3l-val.dts new file mode 100644 index 000000000000..86d7c58fe81d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr3l-val.dts @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM DDR3L Validation board"; + compatible = "fsl,imx8mm-val", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + }; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gd25q16", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&mu { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk-rm67191.dts new file mode 100644 index 000000000000..ff599ffaec4a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk-rm67191.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-ddr4-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts new file mode 100644 index 000000000000..618caf8baf6c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8mm-evk.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; + + leds { + pinctrl-0 = <&pinctrl_gpio_led_2>; + + status { + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + imx8mm-evk { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + + pinctrl_gpio_led_2: gpioled2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +®_sd1_vmmc { + status = "disabled"; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + cap-power-off-card; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * DDR4 board is same to the RevB board, configure + * PCIe REFCLK to internal PLL. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-qca9377-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-qca9377-evk.dts new file mode 100644 index 000000000000..e1339640d56b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-qca9377-evk.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8mm-ddr4-evk.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK with QCA9377-3 WIFI/BT board"; +}; + +®_sd1_vmmc { + status = "okay"; +}; + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + vmmc-supply = <®_sd1_vmmc>; + /delete-property/ mmc-pwrseq; + /delete-property/ cap-power-off-card; + + brcmf: bcrmf@1 { + status = "disabled"; + }; +}; + +&usdhc1_pwrseq { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-val.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-val.dts new file mode 100644 index 000000000000..797f21d166fb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-val.dts @@ -0,0 +1,541 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM DDR4 validation board"; + compatible = "fsl,imx8mm-val", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_typec2: typec2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x159 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu256aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + typec1_ptn5110: tcpci@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8>; + /* Only can sink 5V for safe */ + max-snk-mv = <5000>; + max-snk-ma = <3000>; + op-snk-mw = <10000>; + max-snk-mw = <15000>; + port-type = "drp"; + default-role = "sink"; + status = "okay"; + }; + + typec2_ptn5110: tcpci@52 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec2>; + reg = <0x52>; + interrupt-parent = <&gpio2>; + interrupts = <12 8>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8>; + /* Only can sink 5V for safe */ + max-snk-mv = <5000>; + max-snk-ma = <3000>; + op-snk-mw = <10000>; + max-snk-mw = <15000>; + port-type = "drp"; + default-role = "sink"; + status = "disabled"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&mu { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + extcon = <0>, <&typec1_ptn5110>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "otg"; + extcon = <0>, <&typec2_ptn5110>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak4497.dts new file mode 100644 index 000000000000..438856d84d64 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak4497.dts @@ -0,0 +1,78 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + imx8mm-evk { + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1_SRC>, + <&clk IMX8MM_CLK_SAI1_DIV>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <0>, <22579200>; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0x11>; + dmas = <&sdma2 0 26 0>, <&sdma2 1 26 0>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak5558.dts new file mode 100644 index 000000000000..0268b09a2755 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak5558.dts @@ -0,0 +1,32 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + sound-ak5558 { + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-audio-tdm.dts new file mode 100644 index 000000000000..fc1826bb90cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-audio-tdm.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk-ak5558.dts" + +/ { + sound-ak4458 { + fsl,tdm; + }; + + sound-ak5558 { + fsl,tdm; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-m4.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-m4.dts new file mode 100644 index 000000000000..52bf4db5b0a1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-m4.dts @@ -0,0 +1,85 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mq-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + fsl,enable-lpa; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "ak4497-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + +}; + +/* + * ATTENTION: M4 may use IPs like below + * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 + */ + +&i2c3 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&sdma1{ + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-revb-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-revb-rm67191.dts new file mode 100644 index 000000000000..02c2c0430a14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-revb-rm67191.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk-revb.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-revb.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-revb.dts new file mode 100644 index 000000000000..c2f89aa7002c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-revb.dts @@ -0,0 +1,32 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mm-evk.dts" + +/ { + model = "FSL i.MX8MM EVK RevB board"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-rm67191.dts new file mode 100644 index 000000000000..d7c17e33ffdf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-rm67191.dts @@ -0,0 +1,35 @@ +#include "fsl-imx8mm-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-root.dts new file mode 100644 index 000000000000..2e91fc27471d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-root.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +/delete-node/ &gpc; + +&CPU_SLEEP { + /* We are not using GPC for now, need set 0 to avoid hang */ + /delete-property/ compatible; + /*arm,psci-suspend-param = <0x0>;*/ +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&{/reserved-memory} { + + ivshmem_reserved: ivshmem@0xbbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@0xbba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@0xbb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@0xbb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@0xb7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + inmate_reserved: inmate@0xb3c00000 { + no-map; + reg = <0 0xb3c00000 0x0 0x04000000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts new file mode 100644 index 000000000000..2f9f6c660a65 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts @@ -0,0 +1,371 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ DDR3L ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-arm2 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clock-rates = <0>, <0>, <50000000>, <100000000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&dcss { + status = "okay"; + + disp-dev = "hdmi_disp"; +}; + +&hdmi { + compatible = "fsl,imx8mq-dp"; + + dp-lane-mapping = <0x4e>; + dp-link-rate = <0x14>; + dp-num-lanes = <0x4>; + + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts new file mode 100644 index 000000000000..bc6c8b7c2ce1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts @@ -0,0 +1,52 @@ +/* + * Copyright 2017 NXP + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-ddr4-arm2.dts" + +&iomuxc { + imx8mq-arm2 { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts new file mode 100644 index 000000000000..9679a76599fa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts @@ -0,0 +1,363 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ DDR4 ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-arm2 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts new file mode 100644 index 000000000000..b761d4c949e2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts @@ -0,0 +1,95 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + + imx8mq-evk { + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd512: sai1grp_dsd512 { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd", "dsd512"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + pinctrl-2 = <&pinctrl_sai1_dsd512>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL2_OUT>; + assigned-clock-rates = <45158400>; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0x11>; + dmas = <&sdma2 8 26 0>, <&sdma2 9 26 0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-audio-tdm.dts new file mode 100644 index 000000000000..752114f6a064 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-audio-tdm.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + sound-ak4458 { + fsl,tdm; + }; + + sound-ak5558 { + fsl,tdm; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts new file mode 100644 index 000000000000..da8e86582573 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts @@ -0,0 +1,99 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/delete-node/ &ov5640_mipi; +/delete-node/ &ov5640_mipi2; +/delete-node/ &synaptics_dsx_ts; +/delete-node/ &adv_bridge; + +&i2c1 { + ov5640_mipi: ov5640_mipi@1c { + compatible = "ovti,ov5640_mipi"; + reg = <0x1c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + + ov5640_mipi2: ov5640_mipi2@2c { + compatible = "ovti,ov5640_mipi"; + reg = <0x2c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; + + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "disabled"; + }; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + status = "disabled"; + + port { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_adv>; + }; + }; + }; +}; + +&i2c2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535-b3.dts new file mode 100644 index 000000000000..ca1655dbf8de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535-b3.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk-b3.dts" +#include "fsl-imx8mq-evk-dcss-adv7535.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dts new file mode 100644 index 000000000000..3bd1381a834a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" +#include "fsl-imx8mq-evk-dcss-adv7535.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi new file mode 100644 index 000000000000..5c8dd0154398 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi @@ -0,0 +1,79 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&hdmi { + status = "disabled"; +}; + +&dcss { + status = "okay"; + disp-dev = "mipi_disp"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_CLK_25M>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", + "pll", "pll_src1", "pll_src2"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <594000000>, + <800000000>, + <400000000>; + + dcss_disp0: port@0 { + reg = <0>; + + dcss_disp0_mipi_dsi: mipi_dsi { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_disp0_mipi_dsi>; + }; + }; + +}; + +&mipi_dsi_bridge { + status = "okay"; +}; + +&adv_bridge { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191-b3.dts new file mode 100644 index 000000000000..af47a22e9982 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191-b3.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk-b3.dts" +#include "fsl-imx8mq-evk-dcss-rm67191.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts new file mode 100644 index 000000000000..02467af735f5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" +#include "fsl-imx8mq-evk-dcss-rm67191.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi new file mode 100644 index 000000000000..7d124d3d3e30 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi @@ -0,0 +1,131 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&hdmi { + status = "disabled"; +}; + +&dcss { + status = "okay"; + disp-dev = "mipi_disp"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_CLK_25M>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll", + "pll_src1", "pll_src2"; + + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, + <800000000>, + <400000000>; + + dcss_disp0: port@0 { + reg = <0>; + + dcss_disp0_mipi_dsi: mipi_dsi { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_disp0_mipi_dsi>; + }; + }; + +}; + +&mipi_dsi_bridge { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + + display-timings { + timing { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <20>; + hsync-len = <2>; + hback-porch = <34>; + vfront-porch = <10>; + vsync-len = <5>; + vback-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_out>; + }; + }; + }; + + port@2 { + mipi_dsi_bridge_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&iomuxc { + imx8mq-evk { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; + + }; +}; + +&synaptics_dsx_ts { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dp.dts new file mode 100644 index 000000000000..5b50ef5148a3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dp.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&hdmi { + compatible = "fsl,imx8mq-dp"; + + dp-lane-mapping = <0xc6>; + dp-link-rate = <0x14>; + dp-num-lanes = <0x4>; + + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts new file mode 100644 index 000000000000..a695afbf9469 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts @@ -0,0 +1,41 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&resmem { + display_region: imx_ion@1 { + compatible = "imx-ion-pool"; + reg = <0x0 0xe6000000 0 0x18000000>; + }; + + vpu_region: imx_ion@2 { + compatible = "imx-ion-pool"; + reg = <0x0 0xe4000000 0 0x02000000>; + }; +}; + +&imx_ion { + compatible = "fsl,mxc-ion", "linux,ion"; + + ion-display-region { + compatible = "fsl,display-heap", "linux,ion-heap-unmapped"; + memory-region = <&display_region>; + }; + + ion-vpu-region { + compatible = "fsl,vpu-heap", "linux,ion-heap-unmapped"; + memory-region = <&vpu_region>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display-b3.dts new file mode 100644 index 000000000000..b0c7df737dd9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display-b3.dts @@ -0,0 +1,42 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk-lcdif-adv7535-b3.dts" + +/ { + display-subsystem { + status = "okay"; + }; + + sound-hdmi { + status = "okay"; + }; +}; + +&irqsteer_dcss { + status = "okay"; +}; + +&dcss { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&lcdif { + status = "okay"; + max-res = <1280>, <720>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display.dts new file mode 100644 index 000000000000..21616e6c8619 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display.dts @@ -0,0 +1,42 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk-lcdif-adv7535.dts" + +/ { + display-subsystem { + status = "okay"; + }; + + sound-hdmi { + status = "okay"; + }; +}; + +&irqsteer_dcss { + status = "okay"; +}; + +&dcss { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&lcdif { + status = "okay"; + max-res = <1280>, <720>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-edp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-edp.dts new file mode 100644 index 000000000000..5f8ea76166bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-edp.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&hdmi { + compatible = "fsl,imx8mq-dp"; + lane_mapping = <0xc6>; + fsl,edp; + edp_link_rate = <0x6>; + edp_num_lanes = <0x4>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-inmate.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-inmate.dts new file mode 100644 index 000000000000..135a90498fa7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-inmate.dts @@ -0,0 +1,207 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + interrupt-parent = <&gic>; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clocks { + clk_dummy: clock@7 { + compatible = "fixed-clock"; + reg = <7>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + reg = <8>; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "400m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + reg = <9>; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + reg = <10>; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + }; + + display-subsystem { + /delete-property/ compatible; + }; + + pci@bfb00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 109 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbfb00000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; +}; + +/delete-node/ &{/memory@40000000}; + +&clk { + /delete-property/ compatible; +}; + +/delete-node/ &{/cpus/cpu@0}; +/delete-node/ &{/cpus/cpu@1}; +/delete-node/ &{/pmu}; + +/delete-node/ &{/busfreq}; + +/delete-node/ &resmem; + +&mipi_pd { + status = "disabled"; +}; + +&pcie0_pd { + status = "disabled"; +}; + +&usb_otg1_pd { + status = "disabled"; +}; + +&usb_otg2_pd { + status = "disabled"; +}; + +&gpu_pd { + status = "disabled"; +}; + +&vpu_pd { + status = "disabled"; +}; + +&mipi_csi1_pd { + status = "disabled"; +}; + +&mipi_csi2_pd { + status = "disabled"; +}; + +&pcie1_pd { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; +&gpio2 { + status = "disabled"; +}; +&gpio3 { + status = "disabled"; +}; +&gpio4 { + status = "disabled"; +}; +&gpio5 { + status = "disabled"; +}; + +/delete-node/ &tmu; +/delete-node/ &{/thermal-zones}; + +/delete-node/ &irqsteer_dcss; +/delete-node/ &ocotp; +/delete-node/ &snvs; + +&src { + /delete-property/ compatible; +}; + +&dcss { + /delete-property/ interrupt-parent; +}; + +/delete-node/ &gpc; +/delete-node/ &system_counter; +/delete-node/ &imx_ion; +/delete-node/ &pcie0; +/delete-node/ &pcie1; +/delete-node/ &vpu; +/delete-node/ &ddr_pmu0; +/delete-node/ &imx_rpmsg; +/delete-node/ &crypto; +/delete-node/ &caam_sm; +/delete-node/ &caam_snvs; +/delete-node/ &irq_sec_vio; +/delete-node/ &dma_apbh; +/delete-node/ &gpmi; + +&gic { + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ +}; + + +/delete-node/ &iomuxc; + +&uart2 { + clocks = <&osc_25m>, + <&osc_25m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc1 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535-b3.dts new file mode 100644 index 000000000000..00f881834182 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535-b3.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk-b3.dts" +#include "fsl-imx8mq-evk-lcdif-adv7535.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts new file mode 100644 index 000000000000..e02b6a9f742d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" +#include "fsl-imx8mq-evk-lcdif-adv7535.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dtsi new file mode 100644 index 000000000000..c93885da4d55 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dtsi @@ -0,0 +1,71 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + display-subsystem { + status = "disabled"; + }; + + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer_dcss { + status = "disabled"; +}; + +&dcss { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&lcdif { + status = "okay"; + max-res = <1280>, <720>; + + port@0 { + lcdif_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + as_bridge; + sync-pol = <1>; + pwr-delay = <10>; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; +}; + +&mipi_dsi_bridge { + status = "okay"; +}; + +&adv_bridge { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191-b3.dts new file mode 100644 index 000000000000..41146082c64f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191-b3.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk-b3.dts" +#include "fsl-imx8mq-evk-lcdif-rm67191.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts new file mode 100644 index 000000000000..d2c38003b60e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" +#include "fsl-imx8mq-evk-lcdif-rm67191.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi new file mode 100644 index 000000000000..3688aa04cd6d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi @@ -0,0 +1,101 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + display-subsystem { + status = "disabled"; + }; + + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer_dcss { + status = "disabled"; +}; + +&dcss { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&lcdif { + status = "okay"; + max-res = <1080>, <1920>; + + port@0 { + lcdif_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + as_bridge; + sync-pol = <1>; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; +}; + +&mipi_dsi_bridge { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_out>; + }; + }; + }; + + port@2 { + mipi_dsi_bridge_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&iomuxc { + imx8mq-evk { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; + }; +}; + +&synaptics_dsx_ts { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts new file mode 100644 index 000000000000..c0099e3f431b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + }; +}; + +&gpt1 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&pwm4 { + status = "disabled"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&tmu { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; + +&wdog3{ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-mipi-csi2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-mipi-csi2.dts new file mode 100644 index 000000000000..7e4a672708bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-mipi-csi2.dts @@ -0,0 +1,38 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&ov5640_mipi { + status = "disabled"; +}; + +&ov5640_mipi2 { + status = "okay"; +}; + +&csi1_bridge { + status = "disabled"; +}; + +&csi2_bridge { + status = "okay"; +}; + +&mipi_csi_1 { + status = "disabled"; +}; +&mipi_csi_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pcie1-m2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pcie1-m2.dts new file mode 100644 index 000000000000..6b0147673ec7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pcie1-m2.dts @@ -0,0 +1,82 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: + * 1. The DTS file only support i.MX8MQ EVK RevB1/B2 board PCIe M.2 Murata + * 1CQ (Qca6174) WIFI & BT. + * EVK RevB1 rework: + * WIFI rework: fly line from R1436 (near to M.2) to R1459 + * BT rework: ensure R1446,R1447,R1448,R1449 installed on board + * EVK RevB2 rework: no rework + * + * 2. If need to support i.MX8MQ EVK RevA0/A1 board PCIe M.2 Murata 1CQ + * (Qca6174) WIFI & BT, some board rework requirement: + * EVK RevA0 rework: + * WIFI rework: install R1436 for wlreg_on + * EVK RevA0 rework: + * WIFI rework: install R1436 for wlreg_on + * BT rework: fly line from M.2 pin54 to R1437 + * Also, below DTS change requirement: + * / { + * regulators { + * epdev_on: fixedregulator@100 { + * compatible = "regulator-fixed"; + * regulator-min-microvolt = <3300000>; + * regulator-max-microvolt = <3300000>; + * regulator-name = "epdev_on"; + * gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + * enable-active-high; + * }; + * }; + * }; + * + * &iomuxc { + * imx8mq-evk { + * pinctrl_epdev_on: epdevongrp { + * fsl,pins = < + * MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x16 + * >; + * }; + * }; + * }; + * + * &pcie1{ + * pinctrl-names = "default"; + * pinctrl-0 = <&pinctrl_pcie1 &pinctrl_epdev_on>; + * epdev_on-supply = <&epdev_on>; + * }; + * + * &usdhc2 { + * status = "disabled"; + * }; + * + * + * 3. When wifi driver switch to QCA CLD from ATH10K, there have two known issues: + * - QCA CLD driver only support ONE instance. + * - QCA CLD driver don't support PCIe MSI feature. + * So here it has to disable pcie0 port. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie0{ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts new file mode 100644 index 000000000000..24e9c6bd416c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + sound-pdm { + compatible = "fsl,imx-pdm-mic"; + model = "imx-pdm-audio"; + audio-cpu = <&sai3>; + decimation = <64>; + status = "okay"; + }; +}; + +&iomuxc { + imx8mq-evk { + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts new file mode 100644 index 000000000000..5e1d6688b139 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts @@ -0,0 +1,110 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +/delete-node/ &gpc; + +&CPU_SLEEP { + /* We are not using GPC for now, need set 0 to avoid hang */ + arm,psci-suspend-param = <0x0>; +}; + +&clk { + init-on-array = ; +}; + +&iomuxc { + imx8mq-evk { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&resmem { + jh_reserved: jh@0xfdc00000 { + no-map; + reg = <0 0xfdc00000 0x0 0x400000>; + }; + + inmate_reserved: inmate@0xc0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3dc00000>; + }; + + loader_reserved: loader@0xbff00000 { + no-map; + reg = <0 0xbff00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0xbfe00000 { + no-map; + reg = <0 0xbfe00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@0xbfd00000 { + no-map; + reg = <0 0xbfd00000 0x0 0x00100000>; + }; + + pci_reserved: pci@0xbfc00000 { + no-map; + reg = <0 0xbfb00000 0x0 0x00200000>; + }; +}; + +&uart1 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>, + <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_25M>; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc1 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2-hdmi.dts new file mode 100644 index 000000000000..6d1e5c69e4e2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2-hdmi.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-ddr4-arm2.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai_hdmi_tx>; + constraint-rate = <48000>; + protocol = <1>; + hdmi-out; + }; + + sound-amix-sai { + status = "disabled"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + fsl,cec; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&sai7 { + status = "disabled"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai_hdmi_rx { + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts new file mode 100644 index 000000000000..5a8487e26923 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts @@ -0,0 +1,1300 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM DDR4 ARM2"; + compatible = "fsl,imx8qm-arm2", "fsl,imx8qm"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1FD_BCM89359/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1FD_BCM89359/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_b 3 0>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai6>, <&sai7>; + amix-controller = <&amix>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&lvds0_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&lvds1_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_6_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_7_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + imx8qm-arm2 { + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_MLB_SIG_CONN_MLB_SIG 0x21 + SC_P_MLB_CLK_CONN_MLB_CLK 0x21 + SC_P_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; + +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; + status = "okay"; +}; + +&gpio0_mipi_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1_gpio>; + status = "okay"; +}; + +&i2c0_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + power-domains = <&pd_mclk_out0>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "fsl,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "disabled"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + pinctrl-assert-gpios = <&pca9557_d 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&pixel_combiner1 { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pixel_combiner2 { + status = "okay"; +}; + +&prg10 { + status = "okay"; +}; + +&prg11 { + status = "okay"; +}; + +&prg12 { + status = "okay"; +}; + +&prg13 { + status = "okay"; +}; + +&prg14 { + status = "okay"; +}; + +&prg15 { + status = "okay"; +}; + +&prg16 { + status = "okay"; +}; + +&prg17 { + status = "okay"; +}; + +&prg18 { + status = "okay"; +}; + +&dpr3_channel1 { + status = "okay"; +}; + +&dpr3_channel2 { + status = "okay"; +}; + +&dpr3_channel3 { + status = "okay"; +}; + +&dpr4_channel1 { + status = "okay"; +}; + +&dpr4_channel2 { + status = "okay"; +}; + +&dpr4_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90100000 0x0 0x10000>; + status = "okay"; +}; + +&lvds0_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_pwm0>; + status = "okay"; +}; + +&lvds1_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_pwm0>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_adv: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; +}; + +&i2c0_mipi_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + port@1 { + mipi_dsi_bridge2_adv: endpoint { + remote-endpoint = <&adv7535_2_in>; + }; + }; +}; + +&i2c0_mipi_dsi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge2: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_2_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_adv>; + }; + }; + }; +}; + +&vpu_decoder { + core_type = <2>; + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-enet2-tja1100.dtsi new file mode 100644 index 000000000000..410954296779 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-enet2-tja1100.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* fec1 cannot attach to ethphy0 since the PHY address + * conflict with ethphy2. So eth0 should not work. + * There still enable fec1 to share the MDIO bus for fec2 due + * to board limitation. + */ +&fec1 { + /* PHY address should rework to 2 */ + phy-handle = <ðphy2>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + tja110x,refclk_in; + /delete-property/ at803x,eee-disabled; + /delete-property/ at803x,vddio-1p8v; + }; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&clk IMX8QM_ENET1_IPG_CLK>, + <&clk IMX8QM_ENET1_AHB_CLK>, + <&clk IMX8QM_ENET1_REF_50MHZ_CLK>, + <&clk IMX8QM_ENET1_PTP_CLK>, + <&clk IMX8QM_ENET1_TX_CLK>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + /delete-property/ phy-supply; +}; + +&iomuxc { + imx8qm-mek { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT 0x06000020 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER 0x06000020 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-8cam.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-8cam.dts new file mode 100644 index 000000000000..64c530e4ba1f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-8cam.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * MIPI CSI-2 eight cameras dts, + * One MIPI CSI-2 controller connected four cameras + * The first four cameras have enabled in mipi_csi_0. + * Enable the last four cameras in mipi_csi_1 here. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&mipi_csi_1 { + status = "okay"; +}; + +&i2c0_mipi_csi1 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dom0.dts new file mode 100644 index 000000000000..cb009a4b76a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dom0.dts @@ -0,0 +1,331 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" +#include "fsl-imx8qm-xen.dtsi" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + + /* Could be updated by U-Boot */ + module@0 { + bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; + + domu { + /* + * There are 5 MUs, 0A is used by Dom0, 1A is used + * by ATF, so for DomU, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + compatible = "xen,domu"; + /* + * The name entry in VM configuration file + * needs to be same as here. + */ + domain_name = "DomU"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_GPU_1_PID0 + SC_R_GPU_1_PID1 + SC_R_GPU_1_PID2 + SC_R_GPU_1_PID3 + SC_R_LVDS_1 + SC_R_LVDS_1_I2C_0 + SC_R_LVDS_1_PWM_0 + SC_R_DC_1 + SC_R_DC_1_BLIT0 + SC_R_DC_1_BLIT1 + SC_R_DC_1_BLIT2 + SC_R_DC_1_BLIT_OUT + SC_R_UNUSED9 + SC_R_UNUSED10 + SC_R_DC_1_WARP + SC_R_UNUSED11 + SC_R_UNUSED12 + SC_R_DC_1_VIDEO0 + SC_R_DC_1_VIDEO1 + SC_R_DC_1_FRAC0 + SC_R_UNUSED13 + SC_R_DC_1_PLL_0 + SC_R_DC_1_PLL_1 + SC_R_MIPI_1 + SC_R_MIPI_1_I2C_0 + SC_R_MIPI_1_I2C_1 + SC_R_MIPI_1_PWM_0 + SC_R_HDMI + SC_R_HDMI_I2C_0 + SC_R_SDHC_0 + SC_R_USB_0 + SC_R_USB_0_PHY + SC_R_UART_1 + SC_R_DMA_0_CH14 + SC_R_DMA_0_CH15 + SC_R_MU_2A + >; + pads = < + /* i2c1_lvds1 */ + SC_P_LVDS1_I2C1_SCL + SC_P_LVDS1_I2C1_SDA + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + SC_P_EMMC0_RESET_B + /* usb otg */ + SC_P_USB_SS3_TC0 + /* uart1 */ + SC_P_UART1_RX + SC_P_UART1_TX + SC_P_UART1_CTS_B + SC_P_UART1_RTS_B + SC_P_QSPI1A_DQS + >; + }; + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0xd0000000 0 0x28000000>; + linux,cma-default; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>; + }; + + /* Passthrough to domu */ + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + xen,passthrough; + status = "disabled"; + }; + +}; + +&usbotg1_lpcg { + xen,passthrough; +}; + +&sdhc1_lpcg { + xen,passthrough; +}; + +&lpuart1 { + xen,passthrough; +}; + +&lpuart1_lpcg { + xen,passthrough; +}; + +&di_lvds1_lpcg { + xen,passthrough; +}; + +&dc_1_lpcg { + xen,passthrough; +}; + +&edma01 { + #stream-id-cells = <1>; + xen,passthrough; + fsl,sc_rsrc_id = , + ; +}; + +/* SMMU */ +&smmu { + mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>, + <&usdhc1 0x12>, <&usbotg1 0x11>, + <&edma01 0x10>; +}; + +&lvds_region2 { + xen,passthrough; +}; + +&irqsteer_lvds1 { + xen,passthrough; +}; + +&i2c1_lvds1 { + xen,passthrough; +}; + +&ldb2_phy { + xen,passthrough; +}; + +&ldb2 { + xen,passthrough; +}; + +&crypto { + /* Met CAAM failure on A0, disable it first */ + status = "disabled"; +}; + +&dpu2_intsteer { + xen,passthrough; +}; + +&dpu2 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&prg10 { + xen,passthrough; +}; + +&prg11 { + xen,passthrough; +}; + +&prg12 { + xen,passthrough; +}; + +&prg13 { + xen,passthrough; +}; + +&prg14 { + xen,passthrough; +}; + +&prg15 { + xen,passthrough; +}; + +&prg16 { + xen,passthrough; +}; + +&prg17 { + xen,passthrough; +}; + +&prg18 { + xen,passthrough; +}; + +&dpr3_channel1 { + xen,passthrough; +}; + +&dpr3_channel2 { + xen,passthrough; +}; + +&dpr3_channel3 { + xen,passthrough; +}; + +&dpr4_channel1 { + xen,passthrough; +}; + +&dpr4_channel2 { + xen,passthrough; +}; + +&dpr4_channel3 { + xen,passthrough; +}; + +/* GPU */ +&pd_gpu1 { + xen,passthrough; +}; + +&gpu_3d1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d0>; + /delete-property/ reg; + /delete-property/ reg-names; +}; + +&sata { + status = "disabled"; +}; + +&usdhc1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbotg1 { + /* Hack reg */ + reg = <0x0 0x5b0d0000 0x0 0x1000>; + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbmisc1 { + /* Hack */ + /delete-property/ reg; + status = "disabled"; +}; + +&usbphy1 { + reg = <0x0 0x5b100000 0x0 0x1000>; + xen,passthrough; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts new file mode 100644 index 000000000000..13ecc444bca9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts @@ -0,0 +1,630 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QM DOMU"; + compatible = "fsl,imx8qm-lpddr4", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + /delete-node/ aliases; + + aliases { + mmc0 = &usdhc1; + dpu1 = &dpu2; + ldb1 = &ldb2; + serial1 = &lpuart1; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "hvc"; + }; + + memory@80000000 { + device_type = "memory"; + /* Will be updated by U-Boot or XEN TOOL */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + gic: interrupt-controller@3001000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0x0>; + interrupt-controller; + redistributor-stride = <0x20000>; + #redistributor-regions = <0x1>; + reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ + <0x0 0x3020000 0 0x1000000>; /* GICR */ + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + ; + interrupt-parent = <&gic>; + clock-frequency = <8000000>; + }; + + hypervisor { + compatible = "xen,xen-4.11", "xen,xen"; + reg = <0x0 0x38000000 0x0 0x1000000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + passthrough { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + /* emmc node which used if androidboot.storage_type=emmc */ + dev_emmc = "/dev/block/platform/passthrough/15b010000.usdhc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect,avb"; + }; + }; + + vbmeta { + /*we need use FirstStageMountVBootV2 if we enable avb*/ + compatible = "android,vbmeta"; + /*parts means the partition witch can be mount in first stage*/ + parts = "vbmeta,boot,system,vendor"; + }; + }; + }; + + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + fsl,lpcg_base_offset = <0x00000001 0x00000000>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + #include "fsl-imx8qm-device.dtsi" + + mu2: mu@15d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x1 0x5d1d0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + usb_lpcg { + reg = <0x1 0x5b270000 0x0 0x10000>; + }; + + edma01: dma-controller1@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x1 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x1 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; + }; + }; +}; + +/delete-node/ &tsens; +/delete-node/ &thermal_zones; +/delete-node/ &rtc; + +&display { + ports = <&dpu2_disp0>, <&dpu2_disp1>; +}; + +&dpu2_intsteer { + reg = <0x1 0x57000000 0x0 0x10000>; + status = "okay"; +}; + +&prg10 { + reg = <0x1 0x57040000 0x0 0x10000>; + status = "okay"; +}; + +&prg11 { + reg = <0x1 0x57050000 0x0 0x10000>; + status = "okay"; +}; + +&prg12 { + reg = <0x1 0x57060000 0x0 0x10000>; + status = "okay"; +}; + +&prg13 { + reg = <0x1 0x57070000 0x0 0x10000>; + status = "okay"; +}; + +&prg14 { + reg = <0x1 0x57080000 0x0 0x10000>; + status = "okay"; +}; + +&prg15 { + reg = <0x1 0x57090000 0x0 0x10000>; + status = "okay"; +}; + +&prg16 { + reg = <0x1 0x570a0000 0x0 0x10000>; + status = "okay"; +}; + +&prg17 { + reg = <0x1 0x570b0000 0x0 0x10000>; + status = "okay"; +}; + +&prg18 { + reg = <0x1 0x570c0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel1 { + reg = <0x1 0x570d0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel2 { + reg = <0x1 0x570e0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel3 { + reg = <0x1 0x570f0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel1 { + reg = <0x1 0x57100000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel2 { + reg = <0x1 0x57110000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel3 { + reg = <0x1 0x57120000 0x0 0x10000>; + status = "okay"; +}; + +&dpu2 { + reg = <0x1 0x57180000 0x0 0x40000>; + status = "okay"; + + dpu2_disp0: port@0 { + dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { + /delete-property/ remote-endpoint; + }; + }; + dpu2_disp1: port@1 { + reg = <1>; + + dpu2_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb2_lvds0>; + }; + + dpu2_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb2_lvds1>; + }; + }; +}; + +/delete-node/ &hdmi; +/delete-node/ &irqsteer_dsi0; +/delete-node/ &i2c0_mipi_dsi0; +/delete-node/ &mipi_dsi_csr1; +/delete-node/ &mipi_dsi_phy1; +/delete-node/ &mipi_dsi1; +/delete-node/ &mipi_dsi_bridge1; + +&lvds_region2 { + reg = <0x1 0x57240000 0x0 0x10000>; + status = "okay"; +}; + +&ldb2_phy { + reg = <0x1 0x57241000 0x0 0x100>; + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +/delete-node/ &lvds0_pwm; +/delete-node/ &dpu1_intsteer; +/delete-node/ &prg1; +/delete-node/ &prg2; +/delete-node/ &prg3; +/delete-node/ &prg4; +/delete-node/ &prg5; +/delete-node/ &prg6; +/delete-node/ &prg7; +/delete-node/ &prg8; +/delete-node/ &prg9; +/delete-node/ &dpr1_channel1; +/delete-node/ &dpr1_channel2; +/delete-node/ &dpr1_channel3; +/delete-node/ &dpr2_channel1; +/delete-node/ &dpr2_channel2; +/delete-node/ &dpr2_channel3; +/delete-node/ &dpu1; +/delete-node/ &dsp; +/delete-node/ &irqsteer_dsi1; +/delete-node/ &i2c0_mipi_dsi1; +/delete-node/ &mipi_dsi_csr2; +/delete-node/ &mipi_dsi_phy2; +/delete-node/ &mipi_dsi2; +/delete-node/ &mipi_dsi_bridge2; +/delete-node/ &lvds_region1; +/delete-node/ &ldb1_phy; +/delete-node/ &ldb1; +/delete-node/ &lvds1_pwm; +/delete-node/ &camera; +/delete-node/ &adc0; +/delete-node/ &adc1; +/delete-node/ &i2c0; +/delete-node/ &i2c1; +/delete-node/ &i2c2; +/delete-node/ &i2c3; +/delete-node/ &i2c4; +/delete-node/ &i2c0_cm40; +/delete-node/ &i2c0_cm41; +/delete-node/ &irqsteer_hdmi; +/delete-node/ &i2c0_hdmi; + +&irqsteer_lvds1 { + reg = <0x1 0x57240000 0x0 0x1000>; + /delete-property/ interrupt-parent; + status = "okay"; +}; + +/delete-node/ &flexcan1; +/delete-node/ &flexcan2; +/delete-node/ &flexcan3; + +&i2c1_lvds1 { + reg = <0x1 0x57247000 0x0 0x1000>; + status = "okay"; +}; + +/delete-node/ &irqsteer_lvds0; +/delete-node/ &i2c1_lvds0; +/delete-node/ &irqsteer_csi0; +/delete-node/ &i2c0_mipi_csi0; +/delete-node/ &irqsteer_csi1; +/delete-node/ &i2c0_mipi_csi1; +/delete-node/ &lpspi0; +/delete-node/ &lpspi3; +/delete-node/ &lpuart0; + +&lpuart1 { + /delete-property/ interrupt-parent; + reg = <0x1 0x5a070000 0 0x1000>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +/delete-node/ &lpuart2; +/delete-node/ &lpuart3; +/delete-node/ &lpuart4; +/delete-node/ &emvsim0; +/delete-node/ &edma0; +/delete-node/ &edma2; +/delete-node/ &edma3; +/delete-node/ &gpio0; +/delete-node/ &gpio1; +/delete-node/ &gpio2; +/delete-node/ &gpio3; +/delete-node/ &gpio4; +/delete-node/ &gpio5; +/delete-node/ &gpio6; +/delete-node/ &gpio7; +/delete-node/ &gpio0_mipi_csi0; +/delete-node/ &gpio0_mipi_csi1; +/delete-node/ &gpt0; +/delete-node/ &pwm0; +/delete-node/ &pwm1; +/delete-node/ &pwm2; +/delete-node/ &pwm3; +/delete-node/ &pwm4; +/delete-node/ &pwm5; +/delete-node/ &pwm6; +/delete-node/ &pwm7; + +&gpu_3d1 { + reg = <0x0 0x24100000 0 0x40000>; + status = "okay"; +}; + +/delete-node/ &gpu_3d0; + +&imx8_gpu_ss { + /* xen guests have 3GB of low RAM @ 1GB */ + reg = <0x0 0x40000000 0x0 0xc0000000>; + reg-names = "phys_baseaddr"; + cores = <&gpu_3d1>; + status = "okay"; +}; + +/delete-node/ &mlb; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + /*interrupt-parent = <&gic>;*/ + /delete-property/ interrupt-parent; + reg = <0x1 0x5b010000 0x0 0x10000>; +}; + +/delete-node/ &usdhc2; +/delete-node/ &usdhc3; +/delete-node/ &fec1; +/delete-node/ &fec2; + +&usbmisc1 { + reg = <0x1 0x5b0d0200 0x0 0x200>; +}; + +/delete-node/ &usbmisc2; + +&usbphy1 { + reg = <0x1 0x5b100000 0x0 0x200>; +}; + +/delete-node/ &usbh1; +/delete-node/ &usbotg3; +/delete-node/ &usbphynop1; +/delete-node/ &usbphynop2; + +&usbotg1 { + reg = <0x1 0x5b0d0000 0x0 0x200>; + /delete-property/ interrupt-parent; +}; + +/delete-node/ &ddr_pmu0; +/delete-node/ &ddr_pmu1; +/delete-node/ &vpu; +/delete-node/ &acm; +/delete-node/ &esai0; +/delete-node/ &esai1; +/delete-node/ &spdif0; +/delete-node/ &spdif1; +/delete-node/ &sai1; +/delete-node/ &sai0; +/delete-node/ &sai2; +/delete-node/ &sai3; +/delete-node/ &sai_hdmi_rx; +/delete-node/ &sai_hdmi_tx; +/delete-node/ &sai6; +/delete-node/ &sai7; +/delete-node/ &amix; +/delete-node/ &asrc0; +/delete-node/ &asrc1; +/delete-node/ &mqs; +/delete-node/ &flexspi0; + +&dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; +}; + +/delete-node/ &hsio; +/delete-node/ &ocotp; +/delete-node/ &pciea; +/delete-node/ &pcieb; +/delete-node/ &sata; + +/delete-node/ &intmux_cm40; +/delete-node/ &intmux_cm41; +/delete-node/ &imx_rpmsg; +/delete-node/ &crypto; +/delete-node/ &caam_sm; +/delete-node/ &sc_pwrkey; +/delete-node/ &wdog; +/delete-node/ &wu; + +&iomuxc { + imx8qm-mek { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + >; + }; + }; +}; + +&usdhc1 { + /delete-property/ iommus; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts new file mode 100644 index 000000000000..46600260dd41 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts @@ -0,0 +1,46 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-dp"; + audio-cpu = <&sai_hdmi_tx>; + protocol = <1>; + hdmi-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&hdmi { + compatible = "fsl,imx8qm-dp"; + fsl,use_digpll_pclock; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp.dts new file mode 100644 index 000000000000..c9083f7a89bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-dp"; + audio-cpu = <&sai_hdmi_tx>; + protocol = <1>; + hdmi-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi { + compatible = "fsl,imx8qm-dp"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + + dp-lane-mapping = <0x1b>; + dp-link-rate = <0x14>; + dp-num-lanes = <0x4>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts new file mode 100644 index 000000000000..788ff2cff108 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dts new file mode 100644 index 000000000000..42daa8aedb74 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" +#include "fsl-imx8qm-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi-in.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi-in.dts new file mode 100644 index 000000000000..2f60845773c2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi-in.dts @@ -0,0 +1,70 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-lpddr4-arm2-hdmi.dts" + +/ { + sound-hdmi-rx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-rx"; + audio-cpu = <&sai_hdmi_rx>; + protocol = <1>; + hdmi-in; + }; +}; + +/* HDMI RX */ +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + interface = <4 0 2>; /* + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + status = "okay"; +}; + +&isi_2 { + status = "okay"; + fsl,chain_buf; +}; + +&isi_3 { + status = "disabled"; +}; + + +&mipi_csi_0 { + status = "disabled"; +}; + +&i2c0_mipi_csi0 { + status = "disabled"; +}; + +&hdmi_rx { + fsl,cec; + assigned-clocks = <&clk IMX8QM_HDMI_RX_HD_REF_SEL>, + <&clk IMX8QM_HDMI_RX_PXL_SEL>, + <&clk IMX8QM_HDMI_RX_HD_REF_DIV>; + assigned-clock-parents = <&clk IMX8QM_HDMI_RX_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_RX_BYPASS_CLK>; + assigned-clock-rates = <0>, <0>, <400000000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi.dts new file mode 100644 index 000000000000..7cc8944fac60 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi.dts @@ -0,0 +1,107 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai_hdmi_tx>; + constraint-rate = <48000>; + protocol = <1>; + hdmi-out; + }; + + sound-amix-sai { + status = "disabled"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + fsl,no_edid; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&sai7 { + status = "disabled"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai_hdmi_rx { + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hsic.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hsic.dts new file mode 100644 index 000000000000..d2ce4fe3b00d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hsic.dts @@ -0,0 +1,75 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This dts is only for verify USB HSIC function at i.MX8 Debug Board */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + imx8qm-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_usbh1: PD_USBH1 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_usbh1_io: usbh1_io { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_usbh1>; + }; + }; + }; +}; + +&iomuxc { + imx8qm-arm2 { + pinctrl_usb_hsic_idle: usbh1_1 { + fsl,pins = < + SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0xc60000c5 + SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000c5 + >; + }; + + pinctrl_usb_hsic_active: usbh1_2 { + fsl,pins = < + SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000d5 + >; + }; + }; +}; + +&usbotg1 { + ci-disable-lpm; +}; + +/* + * Due to USB HSIC uses the same AHB and 480M with USBOTG1, + * the usbotg1 must be enabled for usbh1 usage. + */ +&usbh1 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usb_hsic_idle>; + pinctrl-1 = <&pinctrl_usb_hsic_active>; + power-domains = <&pd_usbh1_io>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dts new file mode 100644 index 000000000000..2e9572b4d33b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&ldb1 { + fsl,dual-channel; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb2 { + fsl,dual-channel; +}; + +&i2c1_lvds1 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..39bbdad2d6f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,71 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +&i2c1_lvds1 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi-slave.dts new file mode 100644 index 000000000000..c38b3970bb8d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi-slave.dts @@ -0,0 +1,32 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2-lpspi.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + SC_P_SPI3_SCK_DMA_SPI3_SCK 0x0600004c + SC_P_SPI3_SDO_DMA_SPI3_SDO 0x0600004c + SC_P_SPI3_SDI_DMA_SPI3_SDI 0x0600004c + SC_P_SPI3_CS0_DMA_SPI3_CS0 0x0600004c + >; +}; + +&lpspi3 { + pinctrl-0 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + spi-slave; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi.dts new file mode 100644 index 000000000000..844bdda456d4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi.dts @@ -0,0 +1,79 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&iomuxc { + + imx8qm-arm2 { + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + SC_P_SPI0_CS0_LSIO_GPIO3_IO05 0x21 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + SC_P_SPI3_SCK_DMA_SPI3_SCK 0x0600004c + SC_P_SPI3_SDO_DMA_SPI3_SDO 0x0600004c + SC_P_SPI3_SDI_DMA_SPI3_SDI 0x0600004c + SC_P_SPI3_CS0_DMA_SPI3_CS0 0x0600004c + >; + }; + + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <5000000>; + reg = <0>; + }; +}; + +&lpspi3 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts new file mode 100644 index 000000000000..64d0bb2f77ec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts @@ -0,0 +1,198 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + + leds { + status = "disabled"; + }; + + regulators { + + reg_spdif_en: regulator-spdif-en { + compatible = "regulator-fixed"; + regulator-name = "spdif-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_d 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + reg_wm8962: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + reg_bb2: regulator-bb2 { + compatible = "regulator-fixed"; + regulator-name = "bb2-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; + + sound-wm8962 { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&sai0>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + hp-det-gpios = <&gpio5 26 1>; + mic-det-gpios = <&gpio5 27 1>; + codec-master; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + + imx8qm-arm2 { + + pinctrl_spdif0: spdif0grp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + SC_P_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_MQS_L 0xc6000061 + SC_P_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SAI1_RXC_AUD_SAI0_TXD 0xc6000060 + SC_P_SAI1_RXFS_AUD_SAI0_RXD 0xc6000040 + SC_P_SAI1_TXC_AUD_SAI0_TXC 0xc6000040 + SC_P_SPI2_CS1_AUD_SAI0_TXFS 0xc6000040 + + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0xc6000040 + SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 0xc6000040 + SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 0xc6000040 + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0xc6000040 + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + }; +}; + +&i2c0 { + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + DCVDD-supply = <®_wm8962>; + DBVDD-supply = <®_wm8962>; + AVDD-supply = <®_wm8962>; + CPVDD-supply = <®_wm8962>; + MICVDD-supply = <®_wm8962>; + PLLVDD-supply = <®_wm8962>; + SPKVDD1-supply = <®_wm8962>; + SPKVDD2-supply = <®_wm8962>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + amic-mono; + power-domains = <&pd_mclk_out0>; + }; +}; + + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + status = "disabled"; +}; + +&sai1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts new file mode 100644 index 000000000000..8125de8f0579 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts @@ -0,0 +1,205 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + + leds { + status = "disabled"; + }; + + regulators { + + reg_spdif_en: regulator-spdif-en { + compatible = "regulator-fixed"; + regulator-name = "spdif-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_d 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + reg_wm8962: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + reg_bb2: regulator-bb2 { + compatible = "regulator-fixed"; + regulator-name = "bb2-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + status = "disabled"; + }; + + sound-wm8962 { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&sai0>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + hp-det-gpios = <&gpio5 26 1>; + mic-det-gpios = <&gpio5 27 1>; + codec-master; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + + imx8qm-arm2 { + + pinctrl_spdif0: spdif0grp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + SC_P_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_MQS_L 0xc6000061 + SC_P_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SAI1_RXC_AUD_SAI0_TXD 0xc6000060 + SC_P_SAI1_RXFS_AUD_SAI0_RXD 0xc6000040 + SC_P_SAI1_TXC_AUD_SAI0_TXC 0xc6000040 + SC_P_SPI2_CS1_AUD_SAI0_TXFS 0xc6000040 + + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0xc6000040 + SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 0xc6000040 + SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 0xc6000040 + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0xc6000040 + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&i2c0 { + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + DCVDD-supply = <®_wm8962>; + DBVDD-supply = <®_wm8962>; + AVDD-supply = <®_wm8962>; + CPVDD-supply = <®_wm8962>; + MICVDD-supply = <®_wm8962>; + PLLVDD-supply = <®_wm8962>; + SPKVDD1-supply = <®_wm8962>; + SPKVDD2-supply = <®_wm8962>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + amic-mono; + power-domains = <&pd_mclk_out0>; + }; +}; + + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "disabled"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-usb3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-usb3.dts new file mode 100644 index 000000000000..f1f7538bb719 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-usb3.dts @@ -0,0 +1,113 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This dts is only for verify USB3 Type-C Connector */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + imx8qm-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_ptn5150: PD_PTN5150 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_ptn5150_io: ptn5150_io { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_ptn5150>; + }; + }; + }; +}; + + + +&iomuxc { + imx8qm-arm2 { + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_USB_SS3_TC1_DMA_I2C1_SCL 0xc600004c + SC_P_USB_SS3_TC3_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_ptn5150: ptn5150 { + fsl,pins = < + SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021 + >; + }; + }; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + reg = <0x3d>; + power-domains = <&pd_ptn5150_io>; + connect-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + pca9557_a: gpio@18 { + status = "disabled"; + }; + + pca9557_b: gpio@19 { + status = "disabled"; + }; + + pca9557_c: gpio@1b { + status = "disabled"; + }; + + pca9557_d: gpio@1f { + status = "disabled"; + }; + + fxas2100x@20 { + status = "disabled"; + }; + + fxos8700@1d { + status = "disabled"; + }; + + isl29023@44 { + status = "disabled"; + }; + + mpl3115@60 { + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca53.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca53.dts new file mode 100644 index 000000000000..9c42d98899b0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca53.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&A72_0 { + device_type = ""; +}; + +&A72_1 { + device_type = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca72.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca72.dts new file mode 100644 index 000000000000..55e2e8c51637 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca72.dts @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&A53_0 { + device_type = ""; +}; + +&A53_1 { + device_type = ""; +}; + +&A53_2 { + device_type = ""; +}; + +&A53_3 { + device_type = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0-dpu2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0-dpu2.dts new file mode 100644 index 000000000000..492c453db02c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0-dpu2.dts @@ -0,0 +1,784 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/memreserve/ 0x84000000 0x4000000; +/memreserve/ 0x90000000 0x400000; +/memreserve/ 0x90400000 0x2000000; +/memreserve/ 0x92400000 0x2000000; +/memreserve/ 0x94400000 0x1800000; + +#include "fsl-imx8qm-mek.dtsi" +#include "fsl-imx8qm-xen.dtsi" + +/ { + model = "Freescale i.MX8QM MEK DOM0"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + + /* Could be updated by U-Boot */ + module@0 { + bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; + + domu { + /* + * There are 5 MUs, 0A is used by Dom0, 1A is used + * by ATF, so for DomU, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + compatible = "xen,domu"; + /* + * The name entry in VM configuration file + * needs to be same as here. + */ + domain_name = "DomU"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_MU_6A + SC_R_GPU_0_PID0 + SC_R_GPU_0_PID1 + SC_R_GPU_0_PID2 + SC_R_GPU_0_PID3 + SC_R_LVDS_0 + SC_R_LVDS_0_I2C_0 + SC_R_LVDS_0_PWM_0 + SC_R_DC_0 + SC_R_DC_0_BLIT0 + SC_R_DC_0_BLIT1 + SC_R_DC_0_BLIT2 + SC_R_DC_0_BLIT_OUT + SC_R_UNUSED9 + SC_R_UNUSED10 + SC_R_DC_0_WARP + SC_R_UNUSED11 + SC_R_UNUSED12 + SC_R_DC_0_VIDEO0 + SC_R_DC_0_VIDEO1 + SC_R_DC_0_FRAC0 + SC_R_UNUSED13 + SC_R_DC_0_PLL_0 + SC_R_DC_0_PLL_1 + SC_R_MIPI_0 + SC_R_MIPI_0_I2C_0 + SC_R_MIPI_0_I2C_1 + SC_R_MIPI_0_PWM_0 + SC_R_HDMI + SC_R_HDMI_PLL_0 + SC_R_HDMI_PLL_1 + SC_R_HDMI_I2C_0 + SC_R_HDMI_I2S + SC_R_HDMI_RX + SC_R_SDHC_0 + SC_R_USB_0 + SC_R_USB_0_PHY + SC_R_UART_1 + SC_R_DMA_0_CH14 + SC_R_DMA_0_CH15 + SC_R_MU_2A + /* pcie */ + SC_R_PCIE_B + SC_R_PCIE_A + SC_R_SERDES_0 + SC_R_HSIO_GPIO + /*vpu*/ + SC_R_VPU + SC_R_VPU_PID0 + SC_R_VPU_PID1 + SC_R_VPU_PID2 + SC_R_VPU_PID3 + SC_R_VPU_PID4 + SC_R_VPU_PID5 + SC_R_VPU_PID6 + SC_R_VPU_PID7 + SC_R_VPU_DEC_0 + SC_R_VPU_ENC_0 + SC_R_VPU_ENC_1 + SC_R_VPU_TS_0 + SC_R_VPU_MU_0 + SC_R_VPU_MU_1 + SC_R_VPU_MU_2 + SC_R_VPU_MU_3 + /* crypto */ + SC_R_CAAM_JR2 + SC_R_CAAM_JR2_OUT + SC_R_CAAM_JR3 + SC_R_CAAM_JR3_OUT + /* Camera */ + SC_R_ISI_CH0 + SC_R_ISI_CH1 + SC_R_ISI_CH2 + SC_R_ISI_CH3 + SC_R_MIPI_0 + SC_R_MIPI_0_PWM_0 + SC_R_MIPI_0_I2C_0 + SC_R_MIPI_0_I2C_1 + SC_R_CSI_0 + SC_R_CSI_0_PWM_0 + SC_R_CSI_0_I2C_0 + /* usbotg3 */ + SC_R_USB_2 + SC_R_USB_2_PHY + >; + pads = < + /* i2c1_lvds1 */ + SC_P_LVDS1_I2C1_SCL + SC_P_LVDS1_I2C1_SDA + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + SC_P_EMMC0_RESET_B + /* usb otg */ + SC_P_USB_SS3_TC0 + /* uart1 */ + SC_P_UART1_RX + SC_P_UART1_TX + SC_P_UART1_CTS_B + SC_P_UART1_RTS_B + SC_P_QSPI1A_DQS + /* pciea */ + SC_P_PCIE_CTRL0_CLKREQ_B + SC_P_PCIE_CTRL0_WAKE_B + SC_P_PCIE_CTRL0_PERST_B + SC_P_LVDS1_I2C0_SDA + SC_P_USDHC2_RESET_B + /*usbotgs typec */ + SC_P_QSPI1A_SS0_B + SC_P_USB_SS3_TC3 + SC_P_QSPI1A_DATA0 + /* isl29023 */ + SC_P_USDHC2_WP + + >; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>, + <&gpio1 27 GPIO_ACTIVE_LOW>, + <&gpio4 6 GPIO_ACTIVE_LOW>, + <&gpio4 9 GPIO_ACTIVE_LOW>, + <&gpio4 11 GPIO_ACTIVE_HIGH>, + <&gpio4 19 GPIO_ACTIVE_HIGH>, + <&gpio4 26 GPIO_ACTIVE_HIGH>, + <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0xa0000000 0 0x40000000>; + linux,cma-default; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu2_disp0>, <&dpu2_disp1>; + }; + + /* Passthrough to domu */ + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + xen,passthrough; + status = "disabled"; + }; + + cm41: cm41@1 { + fsl,sc_rsrc_id = , + , + , + , + ; + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + }; + + irqsteer_cm41: irqsteer_cm41@0x51080000 { + reg = <0x0 0x51080000 0x0 0x10000>; + xen,passthrough; + }; + + mu_rpmsg1_b: mu_rpmsg1_b@0x5d2a0000 { + reg = <0x0 0x5d2a0000 0x0 0x10000>; + xen,passthrough; + }; + + decoder_boot_mem: decoder_boot_mem@0x84000000 { + xen,passthrough; + reg = <0 0x84000000 0 0x2000000>; + }; + + encoder_boot_mem: encoder_boot_mem@0x86000000 { + xen,passthrough; + reg = <0 0x86000000 0 0x2000000>; + }; + + rpmsg_reserved_mem: rpmsg_reserved_mem@90000000 { + reg = <0x0 0x90000000 0x0 0x400000>; + xen,passthrough; + }; + + decoder_rpc_mem: decoder_rpc_mem@0x90400000 { + xen,passthrough; + reg = <0 0x90400000 0 0x1000000>; + }; + + encoder_rpc_mem: encoder_rpc_mem@0x91400000 { + xen,passthrough; + reg = <0 0x91400000 0 0x1000000>; + }; + encoder_reserved_mem: encoder_reserved_mem@0x94400000 { + xen,passthrough; + reg = <0 0x94400000 0 0x800000>; + }; + + decoder_str_mem: str_mem@0x94400000 { + xen,passthrough; + reg = <0 0x94400000 0 0x1800000>; + }; + + gpio4_dummy: gpio4_dummy@0{ + /* Passthrough gpio4 interrupt to DomU */ + interrupts = ; + xen,passthrough; + }; +}; + +&mu_rpmsg1 { + xen,passthrough; +}; + +&rpmsg1 { + /* Let xen not create mapping form dom0 */ + /delete-property/ reg; + status = "disabled"; +}; + +&mu_6_lpcg { + xen,passthrough; +}; + +&mu_6_lpcg_b { + xen,passthrough; +}; + +&mu_7_lpcg_b { + xen,passthrough; +}; + +&usbotg1_lpcg { + xen,passthrough; +}; + +&sdhc1_lpcg { + xen,passthrough; +}; + +&lpuart1 { + xen,passthrough; +}; + +&lpuart1_lpcg { + xen,passthrough; +}; + +/* + * DomU CM41 use this, but DomU OS not need this, + * because smmu is enabled for CM41, so need to + *create the lpuart2 mapping in SMMU + */ +&lpuart2 { + xen,passthrough; +}; + +&lpuart2_lpcg { + xen,passthrough; +}; + +&di_lvds0_lpcg { + xen,passthrough; +}; + +&dc_0_lpcg { + xen,passthrough; +}; + +&edma01 { + #stream-id-cells = <1>; + xen,passthrough; + fsl,sc_rsrc_id = , + ; +}; + +/* + * SMMU, for simplity, we put all all the resources needs to programmed + * for VPU under vpu_decoder node, then in cfg file only add vpu_decoder + * in dt_dev is enough. + */ +&smmu { + mmu-masters = <&dpu1 0x13>, <&gpu_3d0 0x15>, + <&usdhc1 0x12>, <&usbotg1 0x11>, + <&edma01 0x10>, <&cm41 0x09>, <&pciea 0x08>, + <&vpu_decoder 0x7>, <&crypto 0x6>, <&isi_0 0x5>, + <&usbotg3 0x4>, <&hdmi 0x3>; +}; + +&lvds_region1 { + xen,passthrough; +}; + +&irqsteer_lvds0 { + xen,passthrough; +}; + +&i2c1_lvds0 { + xen,passthrough; +}; + +&ldb1_phy { + xen,passthrough; +}; + +&ldb1 { + xen,passthrough; +}; + +&dpu1_intsteer { + xen,passthrough; +}; + +&dpu1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&pixel_combiner1 { + xen,passthrough; +}; + +&prg1 { + xen,passthrough; +}; + +&prg2 { + xen,passthrough; +}; + +&prg3 { + xen,passthrough; +}; + +&prg4 { + xen,passthrough; +}; + +&prg5 { + xen,passthrough; +}; + +&prg6 { + xen,passthrough; +}; + +&prg7 { + xen,passthrough; +}; + +&prg8 { + xen,passthrough; +}; + +&prg9 { + xen,passthrough; +}; + +&dpr1_channel1 { + xen,passthrough; +}; + +&dpr1_channel2 { + xen,passthrough; +}; + +&dpr1_channel3 { + xen,passthrough; +}; + +&dpr2_channel1 { + xen,passthrough; +}; + +&dpr2_channel2 { + xen,passthrough; +}; + +&dpr2_channel3 { + xen,passthrough; +}; + +/* GPU */ +&pd_gpu0 { + xen,passthrough; +}; + +&gpu_3d0 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d1>; + /delete-property/ reg; + /delete-property/ reg-names; +}; + +&sata { + status = "disabled"; +}; + +&usdhc1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbotg1 { + /* Hack reg */ + reg = <0x0 0x5b0d0000 0x0 0x1000>; + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbmisc1 { + /* Hack */ + /delete-property/ reg; + status = "disabled"; +}; + +&usbphy1 { + reg = <0x0 0x5b100000 0x0 0x1000>; + xen,passthrough; +}; + +&hsio { + xen,passthrough; +}; + +&hsio_pcie_x2_lpcg { + xen,passthrough; +}; + +&hsio_phy_x2_lpcg { + xen,passthrough; +}; + +&hsio_pcie_x2_crr2_lpcg { + xen,passthrough; +}; + +&hsio_pcie_x1_lpcg { + xen,passthrough; +}; + +&pciea { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + fsl,sc_rsrc_id = ; +}; + +&pcieb { + xen,passthrough; +}; + +&gpio1 { + xen,shared; +}; + +&gpt0 { + /delete-property/ interrupts; + status = "disabled"; +}; + +&gpio4 { + /* + * Use GPT0 interrupt for hack + * This could be removed when interrupt sharing be supported. + */ + interrupts = ; + xen,domu-irq; + xen,shared; +}; + +&dsp { + xen,passthrough; +}; + +&mu_m0 { + xen,passthrough; +}; + +&mu1_m0 { + xen,passthrough; +}; + +&mu2_m0 { + xen,passthrough; +}; + +&vpu_decoder { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&vpu_decoder_csr { + xen,passthrough; +}; + +&vpu_encoder { + iommus = <&smmu>; + #stream-id-cells = <1>; + xen,passthrough; +}; + +&crypto { + xen,passthrough; + iommus = <&smmu>; + #stream-id-cells = <1>; + /* JR1 is not used by Linux */ + fsl,sc_rsrc_id = , , + , ; +}; + +&sec_jr2 { + xen,passthrough; +}; + +&sec_jr3 { + xen,passthrough; +}; + +&caam_sm { + xen,passthrough; +}; + +&i2c0 { + isl29023@44 { + xen,passthrough; + }; + + fxos8700@1e { + xen,passthrough; + }; + + fxas2100x@20 { + xen,passthrough; + }; + + mpl3115@60 { + xen,passthrough; + }; + + typec_ptn5110: typec@50 { + xen,passthrough; + }; +}; + +/* Camera */ +&img_pdma_0_lpcg { + xen,passthrough; +}; + +&img_pdma_1_lpcg { + xen,passthrough; +}; + +&img_pdma_2_lpcg { + xen,passthrough; +}; + +&img_pdma_3_lpcg { + xen,passthrough; +}; + +&mipi_csi_0_lpcg { + xen,passthrough; +}; + +&img_pxl_link_csi0_lpcg { + xen,passthrough; +}; + +&gpio0_mipi_csi0 { + xen,passthrough; +}; + +&irqsteer_csi0 { + xen,passthrough; +}; + +&isi_0 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = , + , + , + ; +}; + +&isi_1 { + xen,passthrough; +}; + +&isi_2 { + xen,passthrough; +}; + +&isi_3 { + xen,passthrough; +}; + +&mipi_csi_0 { + xen,passthrough; +}; + +&i2c0_mipi_csi0 { + xen,passthrough; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +&i2c0_mipi_csi1 { + status = "okay"; +}; + +&usbotg3_lpcg { + xen,passthrough; +}; + +&usbotg3 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +/* hdmi */ +&hdmi { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = , + ; +}; + +&hdmi_rx { + xen,passthrough; +}; + +&irqsteer_hdmi { + xen,passthrough; +}; + +&irqsteer_hdmi_rx { + xen,passthrough; +}; + +&i2c0_hdmi { + xen,passthrough; +}; + +&sai_hdmi_rx { + xen,passthrough; +}; + +&sai_hdmi_tx { + xen,passthrough; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts new file mode 100644 index 000000000000..5fc90cbef0a6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts @@ -0,0 +1,917 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/memreserve/ 0x84000000 0x2000000; +/memreserve/ 0x86000000 0x400000; +/memreserve/ 0x90000000 0x400000; +/memreserve/ 0x90400000 0x1C00000; +/memreserve/ 0x92000000 0x200000; +/memreserve/ 0x92400000 0x2000000; + +#include "fsl-imx8qm-mek.dtsi" +#include "fsl-imx8qm-xen.dtsi" + +/ { + model = "Freescale i.MX8QM MEK DOM0"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + + /* Could be updated by U-Boot */ + module@0 { + bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; + + domu { + /* + * There are 5 MUs, 0A is used by Dom0, 1A is used + * by ATF, so for DomU, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + compatible = "xen,domu"; + /* + * The name entry in VM configuration file + * needs to be same as here. + */ + domain_name = "DomU"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_MU_6A + SC_R_GPU_1_PID0 + SC_R_GPU_1_PID1 + SC_R_GPU_1_PID2 + SC_R_GPU_1_PID3 + SC_R_LVDS_1 + SC_R_LVDS_1_I2C_0 + SC_R_LVDS_1_PWM_0 + SC_R_DC_1 + SC_R_DC_1_BLIT0 + SC_R_DC_1_BLIT1 + SC_R_DC_1_BLIT2 + SC_R_DC_1_BLIT_OUT + SC_R_UNUSED9 + SC_R_UNUSED10 + SC_R_DC_1_WARP + SC_R_UNUSED11 + SC_R_UNUSED12 + SC_R_DC_1_VIDEO0 + SC_R_DC_1_VIDEO1 + SC_R_DC_1_FRAC0 + SC_R_UNUSED13 + SC_R_DC_1_PLL_0 + SC_R_DC_1_PLL_1 + SC_R_MIPI_1 + SC_R_MIPI_1_I2C_0 + SC_R_MIPI_1_I2C_1 + SC_R_MIPI_1_PWM_0 + SC_R_SDHC_0 + SC_R_USB_0 + SC_R_USB_0_PHY + SC_R_UART_1 + SC_R_DMA_0_CH14 + SC_R_DMA_0_CH15 + SC_R_MU_2A + /* pcie */ + SC_R_PCIE_B + SC_R_PCIE_A + SC_R_SERDES_0 + SC_R_HSIO_GPIO + /*vpu*/ + SC_R_VPU + SC_R_VPU_PID0 + SC_R_VPU_PID1 + SC_R_VPU_PID2 + SC_R_VPU_PID3 + SC_R_VPU_PID4 + SC_R_VPU_PID5 + SC_R_VPU_PID6 + SC_R_VPU_PID7 + SC_R_VPU_DEC_0 + SC_R_VPU_ENC_0 + SC_R_VPU_ENC_1 + SC_R_VPU_TS_0 + SC_R_VPU_MU_0 + SC_R_VPU_MU_1 + SC_R_VPU_MU_2 + SC_R_VPU_MU_3 + /* crypto */ + SC_R_CAAM_JR2 + SC_R_CAAM_JR2_OUT + SC_R_CAAM_JR3 + SC_R_CAAM_JR3_OUT + /* Camera */ + SC_R_ISI_CH0 + SC_R_ISI_CH1 + SC_R_ISI_CH2 + SC_R_ISI_CH3 + SC_R_MIPI_0 + SC_R_MIPI_0_PWM_0 + SC_R_MIPI_0_I2C_0 + SC_R_MIPI_0_I2C_1 + SC_R_CSI_0 + SC_R_CSI_0_PWM_0 + SC_R_CSI_0_I2C_0 + /* usbotg3 */ + SC_R_USB_2 + SC_R_USB_2_PHY + /* SAI0 */ + SC_R_DMA_2_CH12 + SC_R_DMA_2_CH13 + SC_R_SAI_0 + /* ESAI0 */ + SC_R_DMA_2_CH6 + SC_R_DMA_2_CH7 + SC_R_ESAI_0 + /* ASRC0 */ + SC_R_DMA_2_CH0 + SC_R_DMA_2_CH1 + SC_R_DMA_2_CH2 + SC_R_DMA_2_CH3 + SC_R_DMA_2_CH4 + SC_R_DMA_2_CH5 + SC_R_ASRC_0 + SC_R_AUDIO_CLK_1 + SC_R_AUDIO_CLK_0 + SC_R_AUDIO_PLL_1 + SC_R_AUDIO_PLL_0 + + SC_R_MCLK_OUT_0 + SC_R_MCLK_OUT_1 + + /* HIFI DSP */ + SC_R_DSP + SC_R_DSP_RAM + SC_R_MU_13B + SC_R_MU_13A + >; + pads = < + /* i2c1_lvds1 */ + SC_P_LVDS1_I2C1_SCL + SC_P_LVDS1_I2C1_SDA + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + SC_P_EMMC0_RESET_B + /* usb otg */ + SC_P_USB_SS3_TC0 + /* uart1 */ + SC_P_UART1_RX + SC_P_UART1_TX + SC_P_UART1_CTS_B + SC_P_UART1_RTS_B + SC_P_QSPI1A_DQS + /* pciea */ + SC_P_PCIE_CTRL0_CLKREQ_B + SC_P_PCIE_CTRL0_WAKE_B + SC_P_PCIE_CTRL0_PERST_B + SC_P_LVDS1_I2C0_SDA + SC_P_USDHC2_RESET_B + /*usbotgs typec */ + SC_P_QSPI1A_SS0_B + SC_P_USB_SS3_TC3 + SC_P_QSPI1A_DATA0 + /* isl29023 */ + SC_P_USDHC2_WP + SC_P_MIPI_CSI0_GPIO0_00 + SC_P_MIPI_CSI0_GPIO0_01 + + /* SAI0 */ + SC_P_SPI0_CS1 + SC_P_SPI2_CS1 + SC_P_SAI1_RXFS + SC_P_SAI1_RXC + + /* ESAI0 */ + SC_P_ESAI0_FSR + SC_P_ESAI0_FST + SC_P_ESAI0_SCKR + SC_P_ESAI0_SCKT + SC_P_ESAI0_TX0 + SC_P_ESAI0_TX1 + SC_P_ESAI0_TX2_RX3 + SC_P_ESAI0_TX3_RX2 + SC_P_ESAI0_TX4_RX1 + SC_P_ESAI0_TX5_RX0 + >; + + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>, + <&gpio1 27 GPIO_ACTIVE_LOW>, + <&gpio1 28 GPIO_ACTIVE_LOW>, + <&gpio4 6 GPIO_ACTIVE_LOW>, + <&gpio4 9 GPIO_ACTIVE_LOW>, + <&gpio4 11 GPIO_ACTIVE_HIGH>, + <&gpio4 19 GPIO_ACTIVE_HIGH>, + <&gpio4 22 GPIO_ACTIVE_LOW>, + <&gpio4 26 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_HIGH>, + <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0xa0000000 0 0x40000000>; + linux,cma-default; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>; + }; + + /* Passthrough to domu */ + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + xen,passthrough; + status = "disabled"; + }; + + cm41: cm41@1 { + fsl,sc_rsrc_id = , + , + , + , + ; + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + /* This will be parased by xen smmu driver */ + init-smmu-bypass; + }; + + irqsteer_cm41: irqsteer_cm41@0x51080000 { + reg = <0x0 0x51080000 0x0 0x10000>; + xen,passthrough; + }; + + mu_rpmsg1_b: mu_rpmsg1_b@0x5d2a0000 { + reg = <0x0 0x5d2a0000 0x0 0x10000>; + xen,passthrough; + }; + + dsp_mu_b: dsp_mu_b@0x5d310000 { + reg = <0x0 0x5d310000 0x0 0x10000>; + xen,passthrough; + }; + + decoder_boot_mem: decoder_boot_mem@0x84000000 { + xen,passthrough; + reg = <0 0x84000000 0 0x2000000>; + }; + + encoder_boot_mem: encoder_boot_mem@0x86000000 { + xen,passthrough; + reg = <0 0x86000000 0 0x400000>; + }; + + rpmsg_reserved_mem: rpmsg_reserved_mem@90000000 { + xen,passthrough; + reg = <0x0 0x90000000 0x0 0x400000>; + }; + + rpmsg_dma_mem: rpmsg_dma_mem@90400000 { + xen,passthrough; + reg = <0x0 0x90400000 0x0 0x1c00000>; + }; + + decoder_rpc_mem: decoder_rpc_mem@0x92000000 { + xen,passthrough; + reg = <0 0x92000000 0 0x200000>; + }; + + encoder_rpc_mem: encoder_rpc_mem@0x92200000 { + xen,passthrough; + reg = <0 0x92200000 0 0x200000>; + }; + + dsp_reserved_mem: dsp@0x92400000 { + xen,passthrough; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved_mem: encoder_reserved_mem@0x94400000 { + xen,passthrough; + reg = <0 0x94400000 0 0x800000>; + }; + + /* This piece memory is used by M41, M40 is not covered */ + m41_mem: m41_mem@0x94400000 { + xen,passthrough; + reg = <0 0x88800000 0 0x7800000>; + }; + + gpio4_dummy: gpio4_dummy@0{ + /* Passthrough gpio4 interrupt to DomU */ + interrupts = ; + xen,passthrough; + }; + + /* Interrupt 33 is not used, use it virtual PL031 */ + rtc0: rtc@23000000 { + interrupts = ; + xen,passthrough; + }; +}; + +&mu_rpmsg1 { + xen,passthrough; +}; + +&rpmsg1 { + /* Let xen not create mapping form dom0 */ + /delete-property/ reg; + status = "disabled"; +}; + +&rpmsg { + /delete-property/ reg; + status = "disabled"; +}; + +&mu_6_lpcg { + xen,passthrough; +}; + +&mu_6_lpcg_b { + xen,passthrough; +}; + +&mu_7_lpcg_b { + xen,passthrough; +}; + +&usbotg1_lpcg { + xen,passthrough; +}; + +&sdhc1_lpcg { + xen,passthrough; +}; + +&lpuart1 { + xen,passthrough; +}; + +&lpuart1_lpcg { + xen,passthrough; +}; + +/* + * DomU CM41 use this, but DomU OS not need this, + * because smmu is enabled for CM41, so need to + *create the lpuart2 mapping in SMMU + */ +&lpuart2 { + xen,passthrough; +}; + +&lpuart2_lpcg { + xen,passthrough; +}; + +&di_lvds1_lpcg { + xen,passthrough; +}; + +&dc_1_lpcg { + xen,passthrough; +}; + +&edma01 { + #stream-id-cells = <1>; + xen,passthrough; +}; + +&edma20 { + #stream-id-cells = <1>; + xen,passthrough; + /* Put edma20 and edma21 resource here */ + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + ; +}; + +&edma21 { + xen,passthrough; +}; + +&edma24 { + xen,passthrough; +}; + +/* + * SMMU, for simplity, we put all all the resources needs to programmed + * for VPU under vpu_decoder node, then in cfg file only add vpu_decoder + * in dt_dev is enough. + */ +&smmu { + mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>, <&edma20 0x14>, + <&usdhc1 0x12>, <&usbotg1 0x11>, + <&edma01 0x10>, <&cm41 0x09>, <&pciea 0x08>, + <&vpu_decoder 0x7>, <&crypto 0x6>, <&isi_0 0x5>, + <&usbotg3 0x4>, <&dsp 0x3>; +}; + +&lvds_region2 { + xen,passthrough; +}; + +&irqsteer_lvds1 { + xen,passthrough; +}; + +&i2c1_lvds1 { + xen,passthrough; +}; + +&ldb2_phy { + xen,passthrough; +}; + +&ldb2 { + xen,passthrough; +}; + +&dpu2_intsteer { + xen,passthrough; +}; + +&dpu2 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&pixel_combiner2 { + xen,passthrough; +}; + +&prg10 { + xen,passthrough; +}; + +&prg11 { + xen,passthrough; +}; + +&prg12 { + xen,passthrough; +}; + +&prg13 { + xen,passthrough; +}; + +&prg14 { + xen,passthrough; +}; + +&prg15 { + xen,passthrough; +}; + +&prg16 { + xen,passthrough; +}; + +&prg17 { + xen,passthrough; +}; + +&prg18 { + xen,passthrough; +}; + +&dpr3_channel1 { + xen,passthrough; +}; + +&dpr3_channel2 { + xen,passthrough; +}; + +&dpr3_channel3 { + xen,passthrough; +}; + +&dpr4_channel1 { + xen,passthrough; +}; + +&dpr4_channel2 { + xen,passthrough; +}; + +&dpr4_channel3 { + xen,passthrough; +}; + +/* GPU */ +&pd_gpu1 { + xen,passthrough; +}; + +&gpu_3d1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d0>; + reg = <0x0 0xa0000000 0x0 0x40000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; +}; + +&sata { + status = "disabled"; +}; + +&usdhc1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbotg1 { + /* Hack reg */ + reg = <0x0 0x5b0d0000 0x0 0x1000>; + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbmisc1 { + /* Hack */ + /delete-property/ reg; + status = "disabled"; +}; + +&usbphy1 { + reg = <0x0 0x5b100000 0x0 0x1000>; + xen,passthrough; +}; + +&hsio { + xen,passthrough; +}; + +&hsio_pcie_x2_lpcg { + xen,passthrough; +}; + +&hsio_phy_x2_lpcg { + xen,passthrough; +}; + +&hsio_pcie_x2_crr2_lpcg { + xen,passthrough; +}; + +&hsio_pcie_x1_lpcg { + xen,passthrough; +}; + +&pciea { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + fsl,sc_rsrc_id = ; +}; + +&pcieb { + xen,passthrough; +}; + +&gpio1 { + xen,shared; +}; + +&gpt0 { + /delete-property/ interrupts; + status = "disabled"; +}; + +&gpio4 { + /* + * Use GPT0 interrupt for hack + * This could be removed when interrupt sharing be supported. + */ + interrupts = ; + xen,domu-irq; + xen,shared; +}; + +&dsp { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&mu13 { + xen,passthrough; +}; + +&mu_m0 { + xen,passthrough; +}; + +&mu1_m0 { + xen,passthrough; +}; + +&mu2_m0 { + xen,passthrough; +}; + +&vpu_decoder { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&vpu_decoder_csr { + xen,passthrough; +}; + +&vpu_encoder { + iommus = <&smmu>; + #stream-id-cells = <1>; + xen,passthrough; +}; + +&{/vpu_encoder@2d000000/core0@1020000} { + xen,passthrough; +}; + +&{/vpu_encoder@2d000000/core1@1040000} { + xen,passthrough; +}; + +&crypto { + xen,passthrough; + iommus = <&smmu>; + #stream-id-cells = <1>; + /* JR1 is not used by Linux */ + fsl,sc_rsrc_id = , , + , ; +}; + +&sec_jr2 { + xen,passthrough; +}; + +&sec_jr3 { + xen,passthrough; +}; + +&caam_sm { + xen,passthrough; +}; + +&i2c0 { + isl29023@44 { + xen,passthrough; + }; + + fxos8700@1e { + xen,passthrough; + }; + + fxas2100x@20 { + xen,passthrough; + }; + + mpl3115@60 { + xen,passthrough; + }; + + typec_ptn5110: typec@50 { + xen,passthrough; + }; +}; + +/* Camera */ +&img_pdma_0_lpcg { + xen,passthrough; +}; + +&img_pdma_1_lpcg { + xen,passthrough; +}; + +&img_pdma_2_lpcg { + xen,passthrough; +}; + +&img_pdma_3_lpcg { + xen,passthrough; +}; + +&mipi_csi_0_lpcg { + xen,passthrough; +}; + +&img_pxl_link_csi0_lpcg { + xen,passthrough; +}; + +&gpio0_mipi_csi0 { + xen,passthrough; +}; + +&irqsteer_csi0 { + xen,passthrough; +}; + +&isi_0 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = , + , + , + ; +}; + +&isi_1 { + xen,passthrough; +}; + +&isi_2 { + xen,passthrough; +}; + +&isi_3 { + xen,passthrough; +}; + +&mipi_csi_0 { + xen,passthrough; +}; + +&i2c0_mipi_csi0 { + xen,passthrough; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +&i2c0_mipi_csi1 { + status = "okay"; +}; + +&usbotg3_lpcg { + xen,passthrough; +}; + +&usbotg3 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +/delete-node/ &{/sound-cs42888}; + +&acm { + xen,passthrough; +}; + +&sai0 { + xen,passthrough; +}; + +&aud_sai_0_lpcg { + xen,passthrough; +}; + +&esai0 { + xen,passthrough; +}; + +&asrc0 { + xen,passthrough; +}; + +&aud_asrc_0_lpcg { + xen,passthrough; +}; + +&aud_esai_0_lpcg { + xen,passthrough; +}; + +&aud_pll_clk0_lpcg { + xen,passthrough; +}; + +&aud_pll_clk1_lpcg { + xen,passthrough; +}; + +&aud_mclkout0_lpcg { + xen,passthrough; +}; + +&aud_mclkout1_lpcg { + xen,passthrough; +}; + +&aud_rec_clk0_lpcg { + xen,passthrough; +}; + +&aud_rec_clk1_lpcg { + xen,passthrough; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-car.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-car.dts new file mode 100644 index 000000000000..1a4e4ff27fe2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-car.dts @@ -0,0 +1,155 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek-domu.dts" + +/* Android Auto use bootargs */ +/delete-node/ &{/reserved-memory/linux,cma}; + +/ { + /* + trusty { + compatible = "android,trusty-smc-v1"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + trusty-virtio { + compatible = "android,trusty-virtio-v1"; + }; + }; + trusty_ipi: interrupt-controller@0 { + compatible = "android,CustomIPI"; + interrupt-controller; + #interrupt-cells = <1>; + }; + */ + + bt_rfkill { + compatible = "fsl,mxc_bt_rfkill"; + bt-power-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + status ="okay"; + }; + + sound-xtor { + compatible = "fsl,imx-audio-xtor"; + model = "xtor-audio"; + cpu-dai = <&sai0>; + status = "okay"; + }; +}; + +&iomuxc { + imx8qm-mek { + pinctrl_mipi_csi0_en_rst: mipi_csi0_en_rst { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000021 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SPI0_CS1_AUD_SAI0_TXC 0x0600004c + SC_P_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c + SC_P_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c + SC_P_SAI1_RXC_AUD_SAI0_TXD 0x0600006c + >; + }; + }; +}; + +/delete-node/ &i2c1_lvds1; +/delete-node/ &i2c0_mipi_csi0; + +&sai0 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_0_MCLK>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&can_rpmsg { + #address-cells = <2>; + #size-cells = <2>; + status = "okay"; + ranges; + i2c0_mipi_csi0: i2c@58226000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi0>; + clocks = <&clk IMX8QM_CSI0_I2C0_CLK>, + <&clk IMX8QM_CSI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_CSI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_csi0_i2c0>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = <1000000>; + pinctrl-0 = <&pinctrl_mipi_csi0_en_rst>; + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + + i2c1_lvds1: i2c@57247000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x57247000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>, + <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds1_i2c0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <400000>; + status = "okay"; + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1-hdmi.dts new file mode 100644 index 000000000000..74641490a692 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1-hdmi.dts @@ -0,0 +1,43 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek-domu-dpu1.dts" + +/ { + /* Sound not enabled */ +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; +}; + +&i2c1_lvds0 { + status = "okay"; +}; + +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + fsl,cec; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts new file mode 100644 index 000000000000..cc866abd07db --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts @@ -0,0 +1,991 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QM DOMU"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + /delete-node/ aliases; + + aliases { + mmc0 = &usdhc1; + dpu0 = &dpu1; + ldb0 = &ldb1; + serial1 = &lpuart1; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + csi0 = &mipi_csi_0; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "hvc"; + }; + + memory@80000000 { + device_type = "memory"; + /* Will be updated by U-Boot or XEN TOOL */ + reg = <0x00000000 0x80000000 0 0x80000000>; + }; + + /* + * The reserved memory will be used when using U-Boot loading android + * image. For booting kernel using xl tool, pass args: + * cma=960M@2400M-3584M + * For the rpmsg_reserved area, need xl tool to create for non-android. + */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + passthrough; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * CM40 rpmsg memory is still for Dom0, the domu.cfg + * not map 0x90000000 - 0x90100000 to DomU. + */ + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@3001000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0x0>; + interrupt-controller; + redistributor-stride = <0x20000>; + #redistributor-regions = <0x1>; + reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ + <0x0 0x3020000 0 0x1000000>; /* GICR */ + interrupts = ; + interrupt-parent = <&gic>; + linux,phandle = <0xfde8>; + phandle = <0xfde8>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + ; + interrupt-parent = <&gic>; + clock-frequency = <8000000>; + }; + + hypervisor { + compatible = "xen,xen-4.11", "xen,xen"; + reg = <0x0 0x38000000 0x0 0x1000000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + passthrough { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + /* emmc node which used if androidboot.storage_type=emmc */ + dev_emmc = "/dev/block/platform/passthrough/5b010000.usdhc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect,avb"; + }; + }; + + vbmeta { + /*we need use FirstStageMountVBootV2 if we enable avb*/ + compatible = "android,vbmeta"; + /*parts means the partition witch can be mount in first stage*/ + parts = "vbmeta,boot,system,vendor"; + }; + }; + }; + + mu_m0: mu_m0@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0"; + reg = <0x0 0x2d000000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; + }; + + mu1_m0: mu1_m0@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x0 0x2d020000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + status = "okay"; + }; + mu2_m0: mu2_m0@2d040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x0 0x2d040000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + status = "okay"; + }; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + reg-csr = <0x2d080000>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qm-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ + reg-names = "vpu_regs"; + power-domains = <&pd_vpu_enc>; + reg-rpc-system = <0x40000000>; + + resolution-max = <1920 1080>; + fps-max = <120>; + status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10a0000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + }; + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + fsl,lpcg_base_offset = <0x00000000 0x00000000>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio4 9 0>; + enable-active-high; + }; + }; + + #include "fsl-imx8qm-device.dtsi" + + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + usb_lpcg { + reg = <0x0 0x5b270000 0x0 0x10000>; + }; + + edma01: dma-controller1@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; + }; + + xen_i2c0: xen_i2c@0 { + compatible = "xen,i2c"; + be-adapter = "5a800000.i2c"; + status = "okay"; + }; + }; +}; + +/delete-node/ &tsens; +/delete-node/ &thermal_zones; +/delete-node/ &rtc; + +&display { + ports = <&dpu1_disp0>, <&dpu1_disp1>; +}; + +&dpu1_intsteer { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pixel_combiner1 { + status = "okay"; +}; + +&hdmi { + status = "disabled"; +}; + +/*/delete-node/ &irqsteer_dsi0;*/ +/*/delete-node/ &i2c0_mipi_dsi0;*/ +/*/delete-node/ &mipi_dsi_csr1;*/ +/*/delete-node/ &mipi_dsi_phy1;*/ +/*/delete-node/ &mipi_dsi1;*/ +/*/delete-node/ &mipi_dsi_bridge1;*/ + +&lvds_region1 { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +/delete-node/ &dpu2_intsteer; +/delete-node/ &prg10; +/delete-node/ &prg11; +/delete-node/ &prg12; +/delete-node/ &prg13; +/delete-node/ &prg14; +/delete-node/ &prg15; +/delete-node/ &prg16; +/delete-node/ &prg17; +/delete-node/ &prg18; +/delete-node/ &dpr3_channel1; +/delete-node/ &dpr3_channel2; +/delete-node/ &dpr3_channel3; +/delete-node/ &dpr4_channel1; +/delete-node/ &dpr4_channel2; +/delete-node/ &dpr4_channel3; +/delete-node/ &dpu2; +/delete-node/ &pixel_combiner2; +/delete-node/ &dsp; +/delete-node/ &irqsteer_dsi1; +/delete-node/ &i2c0_mipi_dsi1; +/delete-node/ &mipi_dsi_csr2; +/delete-node/ &mipi_dsi_phy2; +/delete-node/ &mipi_dsi2; +/delete-node/ &mipi_dsi_bridge2; +/delete-node/ &lvds_region2; +/delete-node/ &ldb2_phy; +/delete-node/ &ldb2; +/delete-node/ &lvds1_pwm; +/*/delete-node/ &camera;*/ +/delete-node/ &adc0; +/delete-node/ &adc1; +/delete-node/ &i2c0; +/delete-node/ &i2c1; +/delete-node/ &i2c2; +/delete-node/ &i2c3; +/delete-node/ &i2c4; +/delete-node/ &i2c0_cm40; +/delete-node/ &i2c0_cm41; +&irqsteer_hdmi { + status = "okay"; +}; +/*/delete-node/ &i2c0_hdmi;*/ +&irqsteer_hdmi_rx { + status = "okay"; +}; +/delete-node/ &irqsteer_lvds1; +/delete-node/ &flexcan1; +/delete-node/ &flexcan2; +/delete-node/ &flexcan3; +/delete-node/ &i2c1_lvds1; +&irqsteer_lvds0 { + /delete-property/ interrupt-parent; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&lvds0_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_pwm0>; + status = "okay"; +}; + +/*/delete-node/ &irqsteer_csi0;*/ +/*/delete-node/ &i2c0_mipi_csi0;*/ +/delete-node/ &irqsteer_csi1; +/delete-node/ &i2c0_mipi_csi1; +/delete-node/ &lpspi0; +/delete-node/ &lpspi3; +/delete-node/ &lpuart0; + +&lpuart1 { + /delete-property/ interrupt-parent; + reg = <0x0 0x5a070000 0 0x1000>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +/delete-node/ &lpuart2; +/delete-node/ &lpuart3; +/delete-node/ &lpuart4; +/delete-node/ &emvsim0; +/delete-node/ &edma0; +/delete-node/ &edma2; +/delete-node/ &edma3; +&gpio0 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio1 { + /delete-property/ power-domains; + status = "okay"; +}; +&gpio2 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio3 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio4 { + /delete-property/ power-domains; + status = "okay"; +}; +&gpio5 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio6 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio7 { + /delete-property/ power-domains; + status = "disabled"; +}; + +/*/delete-node/ &gpio0_mipi_csi0;*/ +/delete-node/ &gpio0_mipi_csi1; +/delete-node/ &gpt0; +/delete-node/ &pwm0; +/delete-node/ &pwm1; +/delete-node/ &pwm2; +/delete-node/ &pwm3; +/delete-node/ &pwm4; +/delete-node/ &pwm5; +/delete-node/ &pwm6; +/delete-node/ &pwm7; + +&gpu_3d0 { + status = "okay"; +}; + +/delete-node/ &gpu_3d1; + +&imx8_gpu_ss { + /* xen guests have 2GB of low RAM @ 2GB */ + reg = <0x0 0x80000000 0x0 0x80000000>; + reg-names = "phys_baseaddr"; + cores = <&gpu_3d0>; + status = "okay"; +}; + +/delete-node/ &mlb; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + /*interrupt-parent = <&gic>;*/ + /delete-property/ interrupt-parent; + reg = <0x0 0x5b010000 0x0 0x10000>; +}; + +/delete-node/ &usdhc2; +/delete-node/ &usdhc3; +/delete-node/ &fec1; +/delete-node/ &fec2; + +&usbmisc1 { + reg = <0x0 0x5b0d0200 0x0 0x200>; +}; + +&usbmisc2 { + status = "okay"; +}; + +&usbphy1 { + reg = <0x0 0x5b100000 0x0 0x200>; +}; + +/delete-node/ &usbh1; + +&usbotg3 { + /delete-property/ interrupt-parent; + dr_mode = "otg"; + extcon = <&typec_ptn5110>; + status = "okay"; +}; + +&usbphynop1 { + status = "okay"; +}; + +/delete-node/ &usbphynop2; + +&usbotg1 { + reg = <0x0 0x5b0d0000 0x0 0x200>; + /delete-property/ interrupt-parent; +}; + +/delete-node/ &ddr_pmu0; +/delete-node/ &ddr_pmu1; +/delete-node/ &vpu; +/delete-node/ &acm; +/delete-node/ &esai0; +/delete-node/ &esai1; +/delete-node/ &spdif0; +/delete-node/ &spdif1; +/delete-node/ &sai1; +/delete-node/ &sai0; +/delete-node/ &sai2; +/delete-node/ &sai3; +/delete-node/ &sai_hdmi_rx; +/delete-node/ &sai_hdmi_tx; +/delete-node/ &sai6; +/delete-node/ &sai7; +/delete-node/ &amix; +/delete-node/ &asrc0; +/delete-node/ &asrc1; +/delete-node/ &mqs; +/delete-node/ &flexspi0; + +&dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; +}; + +/delete-node/ &ocotp; +&pciea { + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; +/delete-node/ &pcieb; +/delete-node/ &sata; + +/delete-node/ &intmux_cm40; +/delete-node/ &intmux_cm41; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90100000 0x0 0x20000>; + status = "okay"; +}; + +&mu_rpmsg1 { + reg = <0x0 0x5d210000 0x0 0x10000>; +}; + +/*/delete-node/ &crypto;*/ +/*/delete-node/ &caam_sm;*/ +/*/delete-node/ &sc_pwrkey;*/ +/delete-node/ &wdog; +/delete-node/ &wu; + +&iomuxc { + imx8qm-mek { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + }; +}; + +&usdhc1 { + /delete-property/ iommus; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&vpu_decoder { + core_type = <2>; + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&xen_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + interrupt-open-drain; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +/* Camera */ +/delete-node/ &isi_4; +/delete-node/ &isi_5; +/delete-node/ &isi_6; +/delete-node/ &isi_7; +/delete-node/ &mipi_csi_1; +/delete-node/ &jpegdec; +/delete-node/ &jpegenc; + +&gpio0_mipi_csi0 { + status = "okay"; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&i2c0_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-hdmi.dts new file mode 100644 index 000000000000..af28b24b77ec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-hdmi.dts @@ -0,0 +1,98 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek-domu.dts" + +/* + * Currently we disable the audio part, since audio in domu not ready. + * This file is reused from fsl-imx8qm-mek-hdmi.dts. + */ + +/ { + passthrough { + /* + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai_hdmi_tx>; + constraint-rate = <48000>; + protocol = <1>; + hdmi-out; + }; + + sound-amix-sai { + status = "disabled"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; + */ + }; +}; + +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + fsl,cec; + status = "okay"; +}; + +/* +&amix { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&sai7 { + status = "disabled"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai_hdmi_rx { + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; + status = "okay"; +}; +*/ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts new file mode 100644 index 000000000000..1ef40bd43df7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts @@ -0,0 +1,1241 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* + * At current stage, M41 is not ready to communicate with XEN, so we + * we need a way to tell XEN uboot is running or linux is running. + * XEN will check the contents of this area. + * So reserve a page at the beginning of GUEST_RAM0_BASE to avoid Linux + * touch this area. + */ +/memreserve/ 0x80000000 0x1000; + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QM DOMU"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + /delete-node/ aliases; + + aliases { + mmc0 = &usdhc1; + dpu1 = &dpu2; + ldb1 = &ldb2; + serial1 = &lpuart1; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + csi0 = &mipi_csi_0; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "hvc"; + }; + + memory@80000000 { + device_type = "memory"; + /* Will be updated by U-Boot or XEN TOOL */ + reg = <0x00000000 0x80000000 0 0x80000000>; + }; + + /* + * The reserved memory will be used when using U-Boot loading android + * image. For booting kernel using xl tool, pass args: + * cma=960M@2400M-3584M + * For the rpmsg_reserved area, need xl tool to create for non-android. + */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + passthrough; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + /* + * CM40 rpmsg memory is still for Dom0, the domu.cfg + * not map 0x90000000 - 0x90100000 to DomU. + */ + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@3001000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0x0>; + interrupt-controller; + redistributor-stride = <0x20000>; + #redistributor-regions = <0x1>; + reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ + <0x0 0x3020000 0 0x1000000>; /* GICR */ + interrupts = ; + interrupt-parent = <&gic>; + linux,phandle = <0xfde8>; + phandle = <0xfde8>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + ; + interrupt-parent = <&gic>; + clock-frequency = <8000000>; + }; + + hypervisor { + compatible = "xen,xen-4.11", "xen,xen"; + reg = <0x0 0x38000000 0x0 0x1000000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + clk0: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + rtc0: rtc@23000000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0x23000000 0x0 0x1000>; + interrupts = ; + clocks = <&clk0>; + clock-names = "apb_pclk"; + }; + + passthrough { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + /* Android Auto Kernel will use this */ + can_rpmsg: can_rpmsg { + compatible = "nxp,imx-can-rpmsg"; + power-domains = <&pd_dc1>; + /* + * fsl,resources is used to open the power of these resources. + * m4 will power down these resources when M4 core give out the control of camera/display. + * rpmsg_can driver will power on these reources once A core take over the control of camera/display. + */ + fsl,resources = ; + fsl,resources-num = <10>; + status = "disabled"; + }; + + firmware { + android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + /* emmc node which used if androidboot.storage_type=emmc */ + dev_emmc = "/dev/block/platform/passthrough/5b010000.usdhc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect,avb"; + }; + }; + + vbmeta { + /*we need use FirstStageMountVBootV2 if we enable avb*/ + compatible = "android,vbmeta"; + /*parts means the partition witch can be mount in first stage*/ + parts = "vbmeta,boot,system,vendor"; + }; + }; + }; + + mu_m0: mu_m0@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0"; + reg = <0x0 0x2d000000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; + }; + + mu1_m0: mu1_m0@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x0 0x2d020000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + status = "okay"; + }; + mu2_m0: mu2_m0@2d040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x0 0x2d040000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + status = "okay"; + }; + + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <13>; + status = "okay"; + }; + + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + reg-csr = <0x2d080000>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qm-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ + reg-names = "vpu_regs"; + power-domains = <&pd_vpu_enc>; + reg-rpc-system = <0x40000000>; + + resolution-max = <1920 1080>; + fps-max = <120>; + status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10a0000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + }; + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + fsl,lpcg_base_offset = <0x00000000 0x00000000>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio4 9 0>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + #include "fsl-imx8qm-device.dtsi" + + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + usb_lpcg { + reg = <0x0 0x5b270000 0x0 0x10000>; + }; + + edma01: dma-controller1@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; + }; + + edma20: dma-controller@591f0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* asrc0 */ + , + , + , + , + ; + interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx"; + status = "okay"; + }; + + edma21: dma-controller@0x59260000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>; /* esai0 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <2>; + interrupts = , /* esai0 */ + ; + interrupt-names = "edma2-chan6-rx", "edma2-chan7-tx"; /* esai0 */ + status = "okay"; + }; + + edma24: dma-controller@0x592c0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>; /* sai0 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <2>; + interrupts = , /* sai0 */ + ; + interrupt-names = "edma2-chan12-rx", "edma2-chan13-tx"; /* sai0 */ + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + xen_i2c0: xen_i2c@0 { + compatible = "xen,i2c"; + be-adapter = "5a800000.i2c"; + status = "okay"; + }; + + xen_i2c1: xen_i2c@1 { + compatible = "xen,i2c"; + be-adapter = "3b230000.i2c"; + status = "okay"; + }; + }; +}; + +/delete-node/ &tsens; +/delete-node/ &thermal_zones; +/delete-node/ &rtc; + +&display { + ports = <&dpu2_disp0>, <&dpu2_disp1>; +}; + +&dpu2_intsteer { + reg = <0x0 0x57000000 0x0 0x10000>; + status = "okay"; +}; + +&prg10 { + reg = <0x0 0x57040000 0x0 0x10000>; + status = "okay"; +}; + +&prg11 { + reg = <0x0 0x57050000 0x0 0x10000>; + status = "okay"; +}; + +&prg12 { + reg = <0x0 0x57060000 0x0 0x10000>; + status = "okay"; +}; + +&prg13 { + reg = <0x0 0x57070000 0x0 0x10000>; + status = "okay"; +}; + +&prg14 { + reg = <0x0 0x57080000 0x0 0x10000>; + status = "okay"; +}; + +&prg15 { + reg = <0x0 0x57090000 0x0 0x10000>; + status = "okay"; +}; + +&prg16 { + reg = <0x0 0x570a0000 0x0 0x10000>; + status = "okay"; +}; + +&prg17 { + reg = <0x0 0x570b0000 0x0 0x10000>; + status = "okay"; +}; + +&prg18 { + reg = <0x0 0x570c0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel1 { + reg = <0x0 0x570d0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel2 { + reg = <0x0 0x570e0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel3 { + reg = <0x0 0x570f0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel1 { + reg = <0x0 0x57100000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel2 { + reg = <0x0 0x57110000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel3 { + reg = <0x0 0x57120000 0x0 0x10000>; + status = "okay"; +}; + +&dpu2 { + reg = <0x0 0x57180000 0x0 0x40000>; + status = "okay"; + + dpu2_disp0: port@0 { + dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { + /delete-property/ remote-endpoint; + }; + }; + dpu2_disp1: port@1 { + reg = <1>; + + dpu2_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb2_lvds0>; + }; + + dpu2_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb2_lvds1>; + }; + }; +}; + +&pixel_combiner2 { + status = "okay"; +}; + +/delete-node/ &hdmi; +/delete-node/ &hdmi_rx; +/delete-node/ &irqsteer_dsi0; +/delete-node/ &i2c0_mipi_dsi0; +/delete-node/ &mipi_dsi_csr1; +/delete-node/ &mipi_dsi_phy1; +/delete-node/ &mipi_dsi1; +/delete-node/ &mipi_dsi_bridge1; + +&lvds_region2 { + reg = <0x0 0x57240000 0x0 0x10000>; + status = "okay"; +}; + +&ldb2_phy { + reg = <0x0 0x57241000 0x0 0x100>; + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +/delete-node/ &lvds0_pwm; +/delete-node/ &dpu1_intsteer; +/delete-node/ &prg1; +/delete-node/ &prg2; +/delete-node/ &prg3; +/delete-node/ &prg4; +/delete-node/ &prg5; +/delete-node/ &prg6; +/delete-node/ &prg7; +/delete-node/ &prg8; +/delete-node/ &prg9; +/delete-node/ &dpr1_channel1; +/delete-node/ &dpr1_channel2; +/delete-node/ &dpr1_channel3; +/delete-node/ &dpr2_channel1; +/delete-node/ &dpr2_channel2; +/delete-node/ &dpr2_channel3; +/delete-node/ &dpu1; +/delete-node/ &pixel_combiner1; + +&dsp { + status = "okay"; +}; + +/delete-node/ &irqsteer_dsi1; +/delete-node/ &i2c0_mipi_dsi1; +/delete-node/ &mipi_dsi_csr2; +/delete-node/ &mipi_dsi_phy2; +/delete-node/ &mipi_dsi2; +/delete-node/ &mipi_dsi_bridge2; +/delete-node/ &lvds_region1; +/delete-node/ &ldb1_phy; +/delete-node/ &ldb1; +/delete-node/ &lvds1_pwm; +/*/delete-node/ &camera;*/ +/delete-node/ &adc0; +/delete-node/ &adc1; +/delete-node/ &i2c0; +/delete-node/ &i2c1; +/delete-node/ &i2c2; +/delete-node/ &i2c3; +/delete-node/ &i2c4; +/delete-node/ &i2c0_cm40; +/delete-node/ &i2c0_cm41; +/delete-node/ &irqsteer_hdmi; +/delete-node/ &irqsteer_hdmi_rx; +/delete-node/ &i2c0_hdmi; + +&irqsteer_lvds1 { + reg = <0x0 0x57240000 0x0 0x1000>; + /delete-property/ interrupt-parent; + status = "okay"; +}; + +/delete-node/ &flexcan1; +/delete-node/ &flexcan2; +/delete-node/ &flexcan3; + +&i2c1_lvds1 { + reg = <0x0 0x57247000 0x0 0x1000>; + status = "okay"; +}; + +/delete-node/ &irqsteer_lvds0; +/delete-node/ &i2c1_lvds0; +/*/delete-node/ &irqsteer_csi0;*/ +/*/delete-node/ &i2c0_mipi_csi0;*/ +/delete-node/ &irqsteer_csi1; +/delete-node/ &i2c0_mipi_csi1; +/delete-node/ &lpspi0; +/delete-node/ &lpspi3; +/delete-node/ &lpuart0; + +&lpuart1 { + /delete-property/ interrupt-parent; + reg = <0x0 0x5a070000 0 0x1000>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +/delete-node/ &lpuart2; +/delete-node/ &lpuart3; +/delete-node/ &lpuart4; +/delete-node/ &emvsim0; +/delete-node/ &edma0; +/delete-node/ &edma2; +/delete-node/ &edma3; +&gpio0 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio1 { + /delete-property/ power-domains; + status = "okay"; +}; +&gpio2 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio3 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio4 { + /delete-property/ power-domains; + status = "okay"; +}; +&gpio5 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio6 { + /delete-property/ power-domains; + status = "disabled"; +}; +&gpio7 { + /delete-property/ power-domains; + status = "disabled"; +}; + +/*/delete-node/ &gpio0_mipi_csi0;*/ +/delete-node/ &gpio0_mipi_csi1; +/delete-node/ &gpt0; +/delete-node/ &pwm0; +/delete-node/ &pwm1; +/delete-node/ &pwm2; +/delete-node/ &pwm3; +/delete-node/ &pwm4; +/delete-node/ &pwm5; +/delete-node/ &pwm6; +/delete-node/ &pwm7; + +&gpu_3d1 { + reg = <0x0 0x54100000 0 0x40000>; + status = "okay"; +}; + +/delete-node/ &gpu_3d0; + +&imx8_gpu_ss { + /* xen guests have 2GB of low RAM @ 2GB */ + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + cores = <&gpu_3d1>; + status = "okay"; +}; + +/delete-node/ &mlb; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + /*interrupt-parent = <&gic>;*/ + /delete-property/ interrupt-parent; + reg = <0x0 0x5b010000 0x0 0x10000>; +}; + +/delete-node/ &usdhc2; +/delete-node/ &usdhc3; +/delete-node/ &fec1; +/delete-node/ &fec2; + +&usbmisc1 { + reg = <0x0 0x5b0d0200 0x0 0x200>; +}; + +&usbmisc2 { + status = "okay"; +}; + +&usbphy1 { + reg = <0x0 0x5b100000 0x0 0x200>; +}; + +/delete-node/ &usbh1; + +&usbotg3 { + /delete-property/ interrupt-parent; + dr_mode = "otg"; + extcon = <&typec_ptn5110>; + status = "okay"; +}; + +&usbphynop1 { + status = "okay"; +}; + +/delete-node/ &usbphynop2; + +&usbotg1 { + reg = <0x0 0x5b0d0000 0x0 0x200>; + /delete-property/ interrupt-parent; +}; + +/delete-node/ &ddr_pmu0; +/delete-node/ &ddr_pmu1; +/delete-node/ &vpu; + +&acm { + status = "okay"; +}; + +&esai0 { + compatible = "fsl,imx8qm-esai"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + dmas = <&edma21 6 0 1>, <&edma21 7 0 0>; + assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + +/delete-node/ &esai1; +/delete-node/ &spdif0; +/delete-node/ &spdif1; +/delete-node/ &sai1; +&sai0 { + dmas = <&edma24 12 0 1>, <&edma24 13 0 0>; +}; +/delete-node/ &sai2; +/delete-node/ &sai3; +/delete-node/ &sai_hdmi_rx; +/delete-node/ &sai_hdmi_tx; +/delete-node/ &sai6; +/delete-node/ &sai7; +/delete-node/ &amix; + +&asrc0 { + dmas = <&edma20 0 0 0>, <&edma20 1 0 0>, <&edma20 2 0 0>, + <&edma20 3 0 1>, <&edma20 4 0 1>, <&edma20 5 0 1>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +/delete-node/ &asrc1; +/delete-node/ &mqs; +/delete-node/ &flexspi0; + +&dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; +}; + +/delete-node/ &ocotp; +&pciea { + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; +/delete-node/ &pcieb; +/delete-node/ &sata; + +/delete-node/ &intmux_cm40; +/delete-node/ &intmux_cm41; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90100000 0x0 0x20000>; + status = "okay"; +}; + +&mu_rpmsg1 { + reg = <0x0 0x5d210000 0x0 0x10000>; +}; + +/*/delete-node/ &crypto;*/ +/*/delete-node/ &caam_sm;*/ +/*/delete-node/ &sc_pwrkey;*/ +/delete-node/ &wdog; +/delete-node/ &wu; + +&iomuxc { + imx8qm-mek { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + }; +}; + +&usdhc1 { + /delete-property/ iommus; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&vpu_decoder { + core_type = <2>; + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&xen_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + interrupt-open-drain; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +&xen_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&gpio4 25 1>; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; + }; +}; + +/* Camera */ +/delete-node/ &isi_4; +/delete-node/ &isi_5; +/delete-node/ &isi_6; +/delete-node/ &isi_7; +/delete-node/ &mipi_csi_1; +/delete-node/ &jpegdec; +/delete-node/ &jpegenc; + +&gpio0_mipi_csi0 { + status = "okay"; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&i2c0_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsi-rm67191.dts new file mode 100644 index 000000000000..4ce6121f1437 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsi-rm67191.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsp.dts new file mode 100644 index 000000000000..3588fe8c16b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsp.dts @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "fsl-imx8qm-mek.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QM_AUD_ASRC_0_IPG>, + <&clk IMX8QM_AUD_ASRC_0_MEM>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QM_ACM_AUD_CLK0_SEL>, + <&clk IMX8QM_ACM_AUD_CLK1_SEL>; + + clock-names = "bus", "mclk", "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + power-domains = <&pd_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma2 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59320000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59330000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + ,/* sai4 */ + ;/* sai5 */ + interrupt-names = "edma2-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan18-tx", "edma2-chan19-rx"; /* sai4, sai5 */ + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + reserved-region = <&dsp_reserved>; + reg = <0x0 0x556e8000 0x0 0x88000>; + clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QM_AUD_ASRC_0_IPG>, + <&clk IMX8QM_AUD_ASRC_0_MEM>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QM_ACM_AUD_CLK0_SEL>, + <&clk IMX8QM_ACM_AUD_CLK1_SEL>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + fixup-offset = <0x4000000>; + power-domains = <&pd_dsp>; +}; + +/delete-node/ &pd_dma2_chan6; +/delete-node/ &pd_dsp_irqsteer; + +&pd_asrc0 { + reg = ; + power-domains =<&pd_dma2_chan5>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan6: PD_ESAI_0_RX { + reg = ; + power-domains =<&pd_asrc0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan7: PD_ESAI_0_TX { + reg = ; + power-domains =<&pd_dma2_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_esai0: PD_AUD_ESAI_0 { + reg = ; + power-domains =<&pd_dma2_chan7>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_irqsteer: PD_DSP_IRQSTEER { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_esai0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_A: PD_DSP_MU_A { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_irqsteer>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_B: PD_DSP_MU_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_A>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_ram: PD_AUD_OCRAM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_B>; + #address-cells = <1>; + #size-cells = <0>; + pd_dsp: PD_AUD_DSP { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_ram>; + }; + }; + }; + }; + }; + }; + }; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-enet2-tja1100.dts new file mode 100644 index 000000000000..817bb62df06a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" +#include "fsl-imx8qm-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi-in.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi-in.dts new file mode 100644 index 000000000000..788680861dae --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi-in.dts @@ -0,0 +1,67 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI IN only dts. + */ + +#include "fsl-imx8qm-mek-hdmi.dts" + +/ { + sound-hdmi-rx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-rx"; + audio-cpu = <&sai_hdmi_rx>; + protocol = <1>; + hdmi-in; + }; +}; + +/* HDMI RX */ +&isi_2 { + interface = <4 0 2>; /* + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + status = "okay"; +}; + +&isi_3 { + /* For HDMI RX 4K chain buf */ + interface = <4 0 2>; + status = "okay"; +}; + +&mipi_csi_0 { + status = "disabled"; +}; + +&i2c0_mipi_csi0 { + status = "disabled"; +}; + +&hdmi_rx { + fsl,cec; + assigned-clocks = <&clk IMX8QM_HDMI_RX_HD_REF_SEL>, + <&clk IMX8QM_HDMI_RX_PXL_SEL>, + <&clk IMX8QM_HDMI_RX_HD_REF_DIV>; + assigned-clock-parents = <&clk IMX8QM_HDMI_RX_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_RX_BYPASS_CLK>; + assigned-clock-rates = <0>, <0>, <400000000>; + status = "okay"; +}; + +&sai_hdmi_rx { + fsl,sai-asynchronous; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts new file mode 100644 index 000000000000..59532f47b2cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts @@ -0,0 +1,88 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-mek.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai_hdmi_tx>; + protocol = <1>; + hdmi-out; + }; + + sound-amix-sai { + status = "disabled"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + fsl,cec; + status = "okay"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts new file mode 100644 index 000000000000..0b7a323cac7a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts @@ -0,0 +1,287 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include +#include "fsl-imx8-ca53.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + /delete-property/ cpu-idle-states; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + /delete-property/ cpu-idle-states; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + imx8qx-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <347>; + + pd_dma0_chan16: PD_UART2_RX { + reg = ; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan17: PD_UART2_TX { + reg = ; + power-domains =<&pd_dma0_chan16>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; + + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, + <&clk IMX8QM_SDHC0_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; + assigned-clock-rates = <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + /*iommus = <&smmu 0x11 0x7f80>;*/ + status = "disabled"; + }; + + /* For early console */ + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART2_CLK>, + <&clk IMX8QM_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan17>; + /* + * dma-names = "tx","rx"; + * dmas = <&edma0 17 0 0>, + * <&edma0 16 0 1>; + */ + status = "disabled"; + }; +}; + +&iomuxc { + imx8qxp-mek { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART0_RTS_B_DMA_UART2_RX 0x06000020 + SC_P_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..8c4d450c775a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,71 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +&i2c1_lvds1 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-ov5640.dts new file mode 100644 index 000000000000..fb6ed45254f0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-ov5640.dts @@ -0,0 +1,153 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&iomuxc { + imx8qm-mek { + pinctrl_mipi_csi0: mipicsi0grp{ + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000021 + >; + }; + + pinctrl_mipi_csi1: mipicsi1grp{ + fsl,pins = < + SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000021 + SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0x00000021 + >; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; + +&i2c0_mipi_csi0 { + clock-frequency = <100000>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk IMX8QM_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; + + max9286_mipi@6A { + status = "disabled"; + }; +}; + +&i2c0_mipi_csi1 { + clock-frequency = <100000>; + status = "okay"; + + ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk IMX8QM_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <1>; + pwn-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep_1: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; + + max9286_mipi@6A { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&mipi_csi_1 { + /delete-property/virtual-channel; + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep_1>; + data-lanes = <1 2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts new file mode 100644 index 000000000000..542d83459d09 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts @@ -0,0 +1,119 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_SDHC_0 + SC_R_DMA_0_CH16 + SC_R_DMA_0_CH17 + SC_R_UART_2 + SC_R_MU_2A + >; + pads = < + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + SC_P_EMMC0_RESET_B + /* lpuart2 */ + SC_P_UART0_RTS_B + SC_P_UART0_CTS_B + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@0xfdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@0xfdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0xfd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@0xfd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@0xdf7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&smmu { + /* Jailhouse hypervisor will initialize SMMU and use it. */ + status = "disabled"; +}; + +&usdhc1 { + /* Let U-Boot program SID */ + iommus = <&smmu 0x10 0x7f80>; + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-rpmsg.dts new file mode 100644 index 000000000000..fdcd408b6dba --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-rpmsg.dts @@ -0,0 +1,17 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-rpmsg.dtsi new file mode 100644 index 000000000000..ec35ad5a83e3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-rpmsg.dtsi @@ -0,0 +1,93 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dtsi" + +/delete-node/ &i2c0_cm41; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&gpio4 25 1>; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance, using 2 instance + * 0x90110000 - 0x9011FFFF: audio + */ + vdev-nums = <2>; + reg = <0x0 0x90100000 0x0 0x20000>; + status = "okay"; +}; + +&intmux_cm41 { + status = "disabled"; +}; + +&intmux_cm40 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca53.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca53.dts new file mode 100644 index 000000000000..5c8c4f499948 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca53.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&A72_0 { + device_type = ""; +}; + +&A72_1 { + device_type = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca72.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca72.dts new file mode 100644 index 000000000000..fa2ff24c51ce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca72.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&A53_0 { + device_type = ""; +}; + +&A53_1 { + device_type = ""; +}; + +&A53_2 { + device_type = ""; +}; + +&A53_3 { + device_type = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi new file mode 100644 index 000000000000..5b11bb8337b8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi @@ -0,0 +1,576 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This dtsi is used by dom0 mainly for passthrough devices to domu. + */ +/ { + /delete-node/ thermal-zones; + + /delete-node/ wu; + + /* + * This is just to avoid renaming all other edma0 nodes, so choose + * edma0a and edma0d here. + */ + edma0a: dma-controller0@5a200000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */ + <0x0 0x5a210000 0x0 0x10000>; /* channel1 LPSPI0 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx"; + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma0d: dma-controller0@5a260000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */ + <0x0 0x5a270000 0x0 0x10000>; /* channel7 LPSPI3 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan6-rx", "edma0-chan7-tx"; + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma00: dma-controller0@5a2c0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>; /* channel13 UART0 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx"; + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma01: dma-controller1@5a2e0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma02: dma-controller2@5a300000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ + <0x0 0x5a310000 0x0 0x10000>; /* channel17 UART2 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx"; + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma03: dma-controller3@5a320000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ + <0x0 0x5a330000 0x0 0x10000>; /* channel19 UART3 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan18-rx", "edma0-chan19-tx"; + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma04: dma-controller4@5a340000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ + <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan20-rx", "edma0-chan21-tx"; + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma20: dma-controller@59200000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* asrc0 */ + , + , + , + , + ; + interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx"; + fsl,sc_rsrc_id = , + , + , + , + , + ; + status = "okay"; + }; + + edma21: dma-controller@0x59260000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>; /* esai0 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <2>; + interrupts = , /* esai0 */ + ; + interrupt-names = "edma2-chan6-rx", "edma2-chan7-tx"; /* esai0 */ + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma22: dma-controller@0x59280000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>; /* spdif0 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <2>; + interrupts = , /* spdif0 */ + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx"; /* spdif0 */ + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma23: dma-controller@0x592a0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x592A0000 0x0 0x10000>, /* spdif1 rx */ + <0x0 0x592B0000 0x0 0x10000>; /* spdif1 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <2>; + interrupts = , /* spdif1 */ + ; + interrupt-names = "edma2-chan10-rx", "edma2-chan11-tx"; /* spdif1 */ + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma24: dma-controller@0x592c0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>; /* sai0 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <2>; + interrupts = , /* sai0 */ + ; + interrupt-names = "edma2-chan12-rx", "edma2-chan13-tx"; /* sai0 */ + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma25: dma-controller@0x592e0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>; /* sai1 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <2>; + interrupts = , /* sai1 */ + ; + interrupt-names = "edma2-chan14-rx", "edma2-chan15-tx"; /* sai1 */ + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + edma26: dma-controller@0x59320000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59320000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59330000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <2>; + interrupts = , /* sai4 */ + ; /* sai5 */ + interrupt-names = "edma2-chan18-rx", "edma2-chan19-tx"; /* sai1 */ + fsl,sc_rsrc_id = , + ; + status = "okay"; + }; + + usbotg1_lpcg: usbotg1_lpcg@5b270000 { + compatible = "fsl,imx8qm-usbotg1-lpcg"; + reg = <0x0 0x5b270000 0x0 0x10000>; + }; + + usbotg3_lpcg: usbotg3_lpcg@5b280000 { + reg = <0x0 0x5b280000 0x0 0x1000>; + }; + + sdhc1_lpcg: sdhc1_lpcg@5b200000 { + compatible = "fsl,imx8qm-lpuart-lpcg"; + reg = <0x0 0x5b200000 0x0 0x10000>; + }; + + lpuart1_lpcg: lpcg@5a470000 { + compatible = "fsl,imx8qm-lpuart-lpcg"; + reg = <0x0 0x5a470000 0x0 0x10000>; + }; + + lpuart2_lpcg: lpcg@5a480000 { + compatible = "fsl,imx8qm-lpuart-lpcg"; + reg = <0x0 0x5a480000 0x0 0x10000>; + }; + + di_lvds0_lpcg: lpcg@56243000 { + compatible = "fsl,imx8qm-di-lvds0-lpcg"; + reg = <0x0 0x56243000 0x0 0x1000>; + }; + + di_lvds1_lpcg: lpcg@57243000 { + compatible = "fsl,imx8qm-di-lvds1-lpcg"; + reg = <0x0 0x57243000 0x0 0x1000>; + }; + + dc_0_lpcg: lpcg@56010000 { + compatible = "fsl,imx8qm-dc0-lpcg"; + reg = <0x0 0x56010000 0x0 0x10000>; + }; + + dc_1_lpcg: lpcg@57010000 { + compatible = "fsl,imx8qm-dc1-lpcg"; + reg = <0x0 0x57010000 0x0 0x10000>; + }; + + mu_5_lpcg: lpcg@5d600000 { + compatible = "fsl,imx8qm-mu-lpcg"; + reg = <0x0 0x5d600000 0x0 0x10000>; + }; + + mu_6_lpcg: lpcg@5d610000 { + compatible = "fsl,imx8qm-mu-lpcg"; + reg = <0x0 0x5d610000 0x0 0x10000>; + }; + + mu_5_lpcg_b: lpcg@5d690000 { + compatible = "fsl,imx8qm-mu-lpcg"; + reg = <0x0 0x5d690000 0x0 0x10000>; + }; + + mu_6_lpcg_b: lpcg@5d6a0000 { + compatible = "fsl,imx8qm-mu-lpcg"; + reg = <0x0 0x5d6a0000 0x0 0x10000>; + }; + + mu_7_lpcg_b: lpcg@5d6b0000 { + compatible = "fsl,imx8qm-mu-lpcg"; + reg = <0x0 0x5d6b0000 0x0 0x10000>; + }; + + hsio_pcie_x2_lpcg: hsio_pcie_x2_lpcg@5f050000 { + reg = <0x0 0x5f050000 0x0 0x10000>; + }; + + hsio_pcie_x1_lpcg: hsio_pcie_x1_lpcg@5f060000 { + reg = <0x0 0x5f060000 0x0 0x10000>; + }; + + hsio_phy_x2_lpcg: hsio_phy_x2_lpcg@5f080000 { + reg = <0x0 0x5f080000 0x0 0x10000>; + }; + + hsio_pcie_x2_crr2_lpcg: hsio_phy_x2_lpcg@5f0c0000 { + reg = <0x0 0x5f0c0000 0x0 0x10000>; + }; + + mipi_csi_0_lpcg: mipi_csi_0_lpcg@58223000 { + reg = <0x0 0x58223000 0x0 0x1000>; + }; + + img_pxl_link_csi0_lpcg: img_pxl_link_csi0_lpcg@58580000 { + reg = <0x0 0x58580000 0x0 0x1000>; + }; + + img_pdma_0_lpcg: img_pdma_0_lpcg@58500000 { + reg = <0x0 0x58500000 0x0 0x1000>; + }; + + img_pdma_1_lpcg: img_pdma_1_lpcg@58510000 { + reg = <0x0 0x58510000 0x0 0x1000>; + }; + + img_pdma_2_lpcg: img_pdma_2_lpcg@58520000 { + reg = <0x0 0x58520000 0x0 0x1000>; + }; + + img_pdma_3_lpcg: img_pdma_3_lpcg@58530000 { + reg = <0x0 0x58530000 0x0 0x1000>; + }; + + vpu_decoder_csr: vpu_decoder_csr@0x2d080000 { + reg = <0x0 0x2d080000 0x0 0x1000>; + }; + + /* hdmi */ + di_hdmi_lpcg: di_hdmi_lpcg@0x56263000 { + reg = <0x0 0x56263000 0x0 0x1000>; + }; + + rx_hdmi_lpcg: rx_hdmi_lpcg@0x58263000 { + reg = <0x0 0x58263000 0x0 0x1000>; + }; + + img_pxl_link_hdmi_lpcg: img_pxl_link_hdmi_lpcg@0x585a0000 { + reg = <0x0 0x585a0000 0x0 0x1000>; + }; + + aud_hdmi_rx_sai_0_lpcg: aud_hdmi_rx_sai_0_lpcg@0x59480000 { + reg = <0x0 0x59480000 0x0 0x1000>; + }; + + aud_hdmi_tx_sai_0_lpcg: aud_hdmi_tx_sai_0_lpcg@0x59490000 { + reg = <0x0 0x59490000 0x0 0x1000>; + }; + + aud_asrc_0_lpcg: aud_asrc_0_lpcg@0x59400000 { + reg = <0x0 0x59400000 0x0 0x1000>; + }; + + aud_esai_0_lpcg: aud_esai_0_lpcg@0x59410000 { + reg = <0x0 0x59410000 0x0 0x1000>; + }; + + aud_pll_clk0_lpcg: aud_pll_clk0_lpcg { + reg = <0x0 0x59d20000 0x0 0x1000>; + }; + + aud_pll_clk1_lpcg: aud_pll_clk1_lpcg { + reg = <0x0 0x59d30000 0x0 0x1000>; + }; + + aud_mclkout0_lpcg: aud_mclkout0_lpcg { + reg = <0x0 0x59d50000 0x0 0x1000>; + }; + + aud_mclkout1_lpcg: aud_mclkout1_lpcg { + reg = <0x0 0x59d60000 0x0 0x1000>; + }; + + aud_rec_clk0_lpcg: aud_rec_clk0_lpcg { + reg = <0x0 0x59d00000 0x0 0x1000>; + }; + + aud_rec_clk1_lpcg: aud_rec_clk1_lpcg { + reg = <0x0 0x59d10000 0x0 0x1000>; + }; + + aud_dsp_lpcg: aud_dsp_lpcg { + reg = <0x0 0x59580000 0x0 0x1000>; + }; + aud_ocram_lpcg: aud_ocram_lpcg { + reg = <0x0 0x59590000 0x0 0x1000>; + }; + + aud_sai_0_lpcg: aud_sai_0_lpcg { + reg = <0x0 0x59440000 0x0 0x1000>; + }; +}; + +/delete-node/ &edma0; +/delete-node/ &edma2; + +&mu { + interrupt-parent = <&gic>; +}; + +&flexcan1 { + interrupt-parent = <&gic>; +}; + +&flexcan2 { + interrupt-parent = <&gic>; +}; + +&flexcan3 { + interrupt-parent = <&gic>; +}; + +&lpspi0 { + interrupt-parent = <&gic>; + dmas = <&edma0a 1 0 0>, <&edma0a 0 0 1>; +}; + +&lpspi3 { + interrupt-parent = <&gic>; + dmas = <&edma0d 7 0 0>, <&edma0d 6 0 1>; +}; + +&lpuart0 { + interrupt-parent = <&gic>; +}; + +&lpuart1 { + interrupt-parent = <&gic>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; +}; + +&lpuart2 { + interrupt-parent = <&gic>; + dmas = <&edma02 17 0 0>, <&edma02 16 0 1>; +}; + +&lpuart3 { + interrupt-parent = <&gic>; + dmas = <&edma03 19 0 0>, <&edma03 18 0 1>; +}; + +&lpuart4 { + interrupt-parent = <&gic>; + dmas = <&edma04 21 0 0>, <&edma04 20 0 1>; +}; + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&fec1 { + interrupt-parent = <&gic>; + /delete-property/ iommus; +}; + +&fec2 { + interrupt-parent = <&gic>; + /delete-property/ iommus; +}; + +&sata { + /delete-property/ iommus; +}; + +&usbotg1 { + interrupt-parent = <&gic>; +}; + +&usbh1 { + interrupt-parent = <&gic>; +}; + +&usbotg3 { + interrupt-parent = <&gic>; +}; + +&smmu { + /* xen only supports legacy bindings for now */ + #iommu-cells = <0>; +}; + +&dpu1 { + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + ; +}; + +&dpu2 { + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + ; +}; + +&esai0 { + dmas = <&edma21 6 0 1>, <&edma21 7 0 0>; +}; + +&spdif0 { + dmas = <&edma22 8 0 5>, <&edma22 9 0 4>; +}; + +&spdif1 { + dmas = <&edma23 10 0 5>, <&edma23 11 0 4>; +}; + +&sai0 { + dmas = <&edma24 12 0 1>, <&edma24 13 0 0>; +}; + +&sai1 { + dmas = <&edma25 14 0 1>, <&edma25 15 0 0>; +}; + +/delete-node/ &sai2; +/delete-node/ &sai3; + +&sai_hdmi_rx { + dmas = <&edma26 18 0 1>; +}; + +&sai_hdmi_tx { + dmas = <&edma26 19 0 0>; +}; + +&asrc0 { + dmas = <&edma20 0 0 0>, <&edma20 1 0 0>, <&edma20 2 0 0>, + <&edma20 3 0 1>, <&edma20 4 0 1>, <&edma20 5 0 1>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts new file mode 100644 index 000000000000..969869097ed5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qp.dtsi" + +#include "fsl-imx8q-arm2.dtsi" + +/ { + model = "Freescale i.MX8QP ARM2"; + compatible = "fsl,imx8qp-arm2", "fsl,imx8qp", "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi new file mode 100644 index 000000000000..97793d66ef23 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QP"; + compatible = "fsl,imx8qp", "fsl,imx8qm"; + + pmu { + interrupt-affinity = <&A72_0>; + }; +}; + +/delete-node/ &A72_1; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&gpu_3d1 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&imx8_gpu_ss {/**/ + operating-points = < + /*nominal*/ 625000 0 + 625000 0 +/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-17x17-val.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-17x17-val.dts new file mode 100644 index 000000000000..dda882ed4e8a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-17x17-val.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +#include "fsl-imx8x-17x17-val.dtsi" + +/ { + model = "Freescale i.MX8QXP 17x17 Validation board"; + compatible = "fsl,imx8qxp-17x17-val", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-ddr3l-val.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-ddr3l-val.dts new file mode 100644 index 000000000000..3e52899599a0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-ddr3l-val.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + model = "Freescale i.MX8QXP DDR3L VALIDATION"; + compatible = "fsl,imx8qxp-ddr3l-val", "fsl,imx8qxp"; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi new file mode 100644 index 000000000000..b664c6f8a215 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, + <&clk IMX8QXP_ENET1_AHB_CLK>, + <&clk IMX8QXP_ENET1_REF_50MHZ_CLK>, + <&clk IMX8QXP_ENET1_PTP_CLK>, + <&clk IMX8QXP_ENET1_TX_CLK>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + /delete-property/ phy-supply; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + tja110x,refclk_in; + }; + }; +}; + +&iomuxc { + imx8qxp-mek { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT 0x06000020 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x06000020 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-a0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-a0.dts new file mode 100644 index 000000000000..264ae77ddbb7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-a0.dts @@ -0,0 +1,24 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&vpu_encoder { + status = "disabled"; +}; + +&vpu_decoder { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dts new file mode 100644 index 000000000000..414cd3231f32 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dts @@ -0,0 +1,61 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsp.dts new file mode 100644 index 000000000000..0a10ac35627c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsp.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ +// Copyright 2017 NXP + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>; + clock-names = "bus", "mclk", "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + power-domains = <&pd_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&codec>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59350000 0x0 0x10000>, + <0x0 0x59370000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + status = "okay"; +}; + +/delete-node/ &pd_dma0_chan6; + +&pd_asrc0 { + reg = ; + power-domains =<&pd_dma0_chan5>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan6: PD_ESAI_0_RX { + reg = ; + power-domains =<&pd_asrc0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan7: PD_ESAI_0_TX { + reg = ; + power-domains =<&pd_dma0_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_esai0: PD_AUD_ESAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan7>; + }; + }; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dts new file mode 100644 index 000000000000..f45a85a736d3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2-enet2.dts" +#include "fsl-imx8qxp-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2.dts new file mode 100644 index 000000000000..7a7c67ff68f7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&esai0 { + status = "disabled"; +}; + +&fec2 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts new file mode 100644 index 000000000000..d1165640116b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts @@ -0,0 +1,67 @@ +/* + * Copyright 2017 NXP + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&iomuxc { + imx8qxp-zebu { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + SC_P_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + SC_P_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + SC_P_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + SC_P_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + SC_P_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + SC_P_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + SC_P_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + SC_P_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + + SC_P_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c + SC_P_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c + SC_P_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c + SC_P_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +/* Disabled the usdhc1/usdhc2 since pin conflict */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts new file mode 100644 index 000000000000..7f3cf7082a93 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2-lpspi.dts" + +/delete-node/&spidev0; + +&lpspi2 { + spi-slave; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi.dts new file mode 100644 index 000000000000..2fb0ea0a413d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi.dts @@ -0,0 +1,78 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&iomuxc { + + imx8qxp-arm2 { + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_ADMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_ADMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_ADMA_SPI0_SDI 0x0600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + SC_P_SPI0_CS0_LSIO_GPIO1_IO08 0x21 + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x0600004c + SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x0600004c + SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x0600004c + SC_P_SPI2_CS0_ADMA_SPI2_CS0 0x0600004c + >; + }; + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <5000000>; + reg = <0>; + }; +}; + +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <10000000>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mlb.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mlb.dts new file mode 100644 index 000000000000..14d164f21c5f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mlb.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&esai0 { + status = "disabled"; +}; + +&mlb { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mqs.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mqs.dts new file mode 100644 index 000000000000..17abb9bc5b67 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mqs.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qxp-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + + imx8qxp-arm2 { + pinctrl_mqs: mqsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_ADMA_MQS_L 0xc6000061 + SC_P_SPDIF0_RX_ADMA_MQS_R 0xc6000061 + >; + }; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-spdif.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-spdif.dts new file mode 100644 index 000000000000..c6622623101b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-spdif.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; +}; + +&iomuxc { + + imx8qxp-arm2 { + + pinctrl_spdif0: spdif0grp { + fsl,pins = < + SC_P_SPDIF0_TX_ADMA_SPDIF0_TX 0xc6000040 + SC_P_SPDIF0_RX_ADMA_SPDIF0_RX 0xc6000040 + >; + }; + + }; +}; + +&esai0 { + status = "disabled"; +}; + +&spdif0 { + compatible = "fsl,imx8qm-spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts new file mode 100644 index 000000000000..8f39af831aef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts @@ -0,0 +1,113 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + regulators { + reg_wm8962: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8962 { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&sai0>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + codec-master; + hp-det-gpios = <&gpio1 2 1>; + mic-det-gpios = <&gpio1 3 1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + imx8qxp-lpddr4-arm2 { + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SAI0_TXFS_ADMA_SAI0_TXFS 0xc6000040 + SC_P_SAI0_TXC_ADMA_SAI0_TXC 0xc6000040 + SC_P_SAI0_TXD_ADMA_SAI0_TXD 0xc6000060 + SC_P_SAI0_RXD_ADMA_SAI0_RXD 0xc6000040 + SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0xc6000040 + SC_P_SPI2_SDI_LSIO_GPIO1_IO02 0xc6000040 + SC_P_SPI2_SCK_LSIO_GPIO1_IO03 0xc6000040 + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + }; +}; + +&i2c0_csi0 { + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + DCVDD-supply = <®_wm8962>; + DBVDD-supply = <®_wm8962>; + AVDD-supply = <®_wm8962>; + CPVDD-supply = <®_wm8962>; + MICVDD-supply = <®_wm8962>; + PLLVDD-supply = <®_wm8962>; + SPKVDD1-supply = <®_wm8962>; + SPKVDD2-supply = <®_wm8962>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + amic-mono; + power-domains = <&pd_mclk_out0>; + }; +}; + +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-a0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-a0.dts new file mode 100755 index 000000000000..c64dda8215f7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-a0.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&vpu_encoder { + status = "disabled"; +}; + +&vpu_decoder { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dom0.dts new file mode 100644 index 000000000000..623b30113dc5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dom0.dts @@ -0,0 +1,90 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/memreserve/ 0x84000000 0x2200000; +/memreserve/ 0x90000000 0x400000; +/memreserve/ 0x90400000 0x400000; +/memreserve/ 0x92400000 0x2000000; + +#include "fsl-imx8qxp-mek.dtsi" +#include "fsl-imx8qxp-xen.dtsi" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + module@0 { + bootargs = "earlycon=xen console=hvc0 root=/dev/mmcblk1p2 rootwait rw"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + /* The size will be override by uboot command */ + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xa0000000 0 0x40000000>; + linux,cma-default; + }; + }; + + /* + * Dom0 memory is from 0x90000000, so add reg to make sure + * the memory is mapped as device, because they are used + * for vpu boot code. + */ + decoder_boot_mem: decoder_boot_mem@0x84000000 { + reg = <0 0x84000000 0 0x2000000>; + }; + + encoder_boot_mem: encoder_boot_mem@0x86000000 { + reg = <0 0x86000000 0 0x200000>; + }; + + rpmsg_reserved_mem: rpmsg_reserved_mem@90000000 { + reg = <0x0 0x90000000 0x0 0x400000>; + }; + + decoder_rpc_mem: decoder_rpc_mem@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + }; + + encoder_rpc_mem: encoder_rpc_mem@0x92200000 { + reg = <0 0x92200000 0 0x200000>; + }; + + dsp_reserved_mem: dsp_reserved_mem@0x92400000 { + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved_mem: encoder_reserved_mem@0x94400000 { + reg = <0 0x94400000 0 0x800000>; + }; + + rtc0: rtc@23000000 { + interrupts = ; + xen,passthrough; + }; +}; + +&imx8_gpu_ss { + /delete-property/ reg; + /delete-property/ reg-names; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsi-rm67191.dts new file mode 100644 index 000000000000..a5debdc6ff7e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsi-rm67191.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpio = <&pca9557_a 6 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpio = <&pca9557_b 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsp.dts new file mode 100644 index 000000000000..70c0fbdd8171 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsp.dts @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "fsl-imx8qxp-mek.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound { + status = "disabled"; + }; + + dspaudio: dspaudio { + compatible = "fsl,dsp-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + status = "okay"; + }; + + sound-dsp { + compatible = "fsl,imx-dsp-audio"; + model = "dsp-audio"; + cpu-dai = <&dspaudio>; + audio-codec = <&cs42888>; + audio-platform = <&dsp>; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59350000 0x0 0x10000>, + <0x0 0x59370000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qxp-dsp"; + reserved-region = <&dsp_reserved>; + reg = <0x0 0x596e8000 0x0 0x88000>; + clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>; + clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3"; + assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd_dsp>; +}; + +/delete-node/ &pd_dma0_chan6; +/delete-node/ &pd_dsp_mu_A; + +&pd_asrc0 { + reg = ; + power-domains =<&pd_dma0_chan5>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan6: PD_ESAI_0_RX { + reg = ; + power-domains =<&pd_asrc0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan7: PD_ESAI_0_TX { + reg = ; + power-domains =<&pd_dma0_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_esai0: PD_AUD_ESAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan7>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_A: PD_DSP_MU_A { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_esai0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_B: PD_DSP_MU_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_A>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_ram: PD_AUD_OCRAM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_B>; + #address-cells = <1>; + #size-cells = <0>; + pd_dsp: PD_AUD_DSP { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_ram>; + }; + }; + }; + }; + }; + }; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <12288000>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2-tja1100.dts new file mode 100644 index 000000000000..d9b3842502f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek-enet2.dts" +#include "fsl-imx8qxp-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts new file mode 100644 index 000000000000..184df3f14ad1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&esai0 { + status = "disabled"; +}; + +&fec2 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-inmate.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-inmate.dts new file mode 100644 index 000000000000..36b23d50af28 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-inmate.dts @@ -0,0 +1,294 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include +#include "fsl-imx8-ca35.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + /delete-property/ cpu-idle-states; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + /delete-property/ cpu-idle-states; + }; + + cpu@2 { + /delete-property/ cpu-idle-states; + }; + + cpu@3 { + /delete-property/ cpu-idle-states; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk: clk { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + imx8qx-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + /*wakeup-irq = <227>;*/ + + pd_dma2_chan12: PD_UART2_RX { + reg = ; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan13: PD_UART2_TX { + reg = ; + power-domains =<&pd_dma2_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; + + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = ; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, + <&clk IMX8QXP_SDHC0_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-rates = <0>, <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + + /* For early console */ + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART2_CLK>, + <&clk IMX8QXP_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma2_chan13>; + /* + * dma-names = "tx","rx"; + * dmas = <&edma2 13 0 0>, + * <&edma2 12 0 1>; + */ + status = "disabled"; + }; + +}; + +&iomuxc { + imx8qxp-mek { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dts new file mode 100755 index 000000000000..aa6d7b27cf1b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&i2c0_mipi_lvds0 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_0_dual_lvds>; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dts new file mode 100755 index 000000000000..14328ef010fb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&i2c0_mipi_lvds1 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dts new file mode 100644 index 000000000000..f855f66e94e5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_0_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds0_in>; + }; + }; + }; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..b23fb2b6fa3d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight0>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&ldb1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lcdif.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lcdif.dts new file mode 100644 index 000000000000..e884a771b76e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lcdif.dts @@ -0,0 +1,97 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + display-subsystem { + status = "disabled"; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&lcdif_backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&adapter_out>; + }; + }; + }; + + seiko_adapter: seiko-adapter { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,seiko-43wvfig"; + bus_mode = <18>; + + port@0 { + reg = <0>; + adapter_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + port@1 { + reg = <1>; + adapter_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + +}; + +&iomuxc { + imx8qxp-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; + +&lcdif_backlight { + status = "okay"; +}; + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + port@0 { + lcdif_out: lcdif-endpoint { + remote-endpoint = <&adapter_in>; + }; + }; +}; + +&pwm_adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_pwm>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds0-it6263.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds0-it6263.dtsi new file mode 100644 index 000000000000..acd6a388cce0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds0-it6263.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds1-it6263.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds1-it6263.dtsi new file mode 100644 index 000000000000..c3088ea63fab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds1-it6263.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + + port { + it6263_1_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640-rpmsg.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640-rpmsg.dts new file mode 100644 index 000000000000..0294a85466de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640-rpmsg.dts @@ -0,0 +1,24 @@ +#include "fsl-imx8qxp-mek-rpmsg.dts" +#include "fsl-imx8qxp-mek-ov5640.dtsi" + +&i2c_rpbus_5 { + ov5640: ov5640@3c { + compatible = "ovti,ov5640_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dts new file mode 100644 index 000000000000..e8d0f1c150ca --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dts @@ -0,0 +1,24 @@ +#include "fsl-imx8qxp-mek.dts" +#include "fsl-imx8qxp-mek-ov5640.dtsi" + +&i2c0_cm40 { + ov5640: ov5640@3c { + compatible = "ovti,ov5640_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dtsi new file mode 100644 index 000000000000..dacf622289a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dtsi @@ -0,0 +1,126 @@ +&iomuxc { + imx8qxp-mek { + pinctrl_mipi_csi0: mipicsi0grp{ + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + SC_P_CSI_D00_CI_PI_D02 0xC0000041 + SC_P_CSI_D01_CI_PI_D03 0xC0000041 + SC_P_CSI_D02_CI_PI_D04 0xC0000041 + SC_P_CSI_D03_CI_PI_D05 0xC0000041 + SC_P_CSI_D04_CI_PI_D06 0xC0000041 + SC_P_CSI_D05_CI_PI_D07 0xC0000041 + SC_P_CSI_D06_CI_PI_D08 0xC0000041 + SC_P_CSI_D07_CI_PI_D09 0xC0000041 + + SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 + SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 + SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + SC_P_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; + }; + }; +}; + +&isi_0 { + interface = <6 0 2>; /* INPUT: 6-PARALLEL CSI */ + parallel_csi; + status = "okay"; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&isi_2 { + interface = <2 0 2>; + status = "okay"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_4 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; + +&i2c0_csi0 { + clock-frequency = <100000>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk IMX8QXP_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; + + max9286_mipi@6A { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-root.dts new file mode 100644 index 000000000000..4c5aac65f60d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-root.dts @@ -0,0 +1,111 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_SDHC_0 + SC_R_DMA_2_CH12 + SC_R_DMA_2_CH13 + SC_R_UART_2 + SC_R_MU_2A + >; + pads = < + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + /* lpuart2 */ + SC_P_UART2_TX + SC_P_UART2_RX + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@0xfdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@0xfdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0xfd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@0xfd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@0xdf7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&usdhc1 { + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dts new file mode 100644 index 000000000000..858827eee055 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dts @@ -0,0 +1,17 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qxp-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi new file mode 100755 index 000000000000..1d8f99294abf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi @@ -0,0 +1,200 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dtsi" + +/delete-node/ &i2c0_cm40; +/delete-node/ &i2c1; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +&i2c_rpbus_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + wlf,shared-lrclk; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 1>; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + }; + }; + }; + +}; + +&i2c_rpbus_12 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_rpbus_14 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "fsl,fxas2100x"; + reg = <0x21>; + interrupt-open-drain; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; +}; + +&i2c_rpbus_15 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio1>; + interrupts = <2 2>; + }; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +&intmux_cm40 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-xen.dtsi new file mode 100644 index 000000000000..2d600d0700c0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-xen.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + /delete-node/ wu; +}; + +&usbotg1 { + interrupt-parent = <&gic>; +}; + +&flexcan1 { + interrupt-parent = <&gic>; +}; + +&flexcan2 { + interrupt-parent = <&gic>; +}; + +&flexcan3 { + interrupt-parent = <&gic>; +}; + +&usbotg3 { + interrupt-parent = <&gic>; +}; + +&lpuart0 { + interrupt-parent = <&gic>; +}; + +&lpuart1 { + interrupt-parent = <&gic>; +}; + +&lpuart2 { + interrupt-parent = <&gic>; +}; + +&lpuart3 { + interrupt-parent = <&gic>; +}; + +&fec1 { + interrupt-parent = <&gic>; +}; + +&fec2 { + interrupt-parent = <&gic>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-17x17-val.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-17x17-val.dtsi new file mode 100644 index 000000000000..ac38be4998a6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-17x17-val.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8x-arm2.dtsi" + +/ { + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; + + regulators { + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + imx8qxp-lpddr4-arm2 { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + >; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + /delete-node/ gpio@68; + /delete-node/ typec@3d; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + /delete-node/ gpio@18; + /delete-node/ gpio@19; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c0_csi0 { + status = "disabled"; +}; + +&mipi_csi_0 { + status = "disabled"; +}; + +&gpio0_mipi_csi0 { + status = "disabled"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + disable-gpio = <&pca9557_a 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + /delete-node/ mt35xu512aba@0; + + flash0: mt25qu512abb@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu512abb"; + spi-max-frequency = <29000000>; + }; +}; + +&adc0 { + status = "disabled"; +}; + +&usbotg1 { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; -- 2.17.1