From 1a3160ae69f725237752f65ee7bd47f5db4cfc1d Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 6 Sep 2016 13:19:37 +0800 Subject: [PATCH] MLK-13188-2 dts: imx6ull: change the usdhc root clock to 396MHz Due to the errata ERR010450 limit, this patch change the imx6ull usdhc root clock to 132MHz in soc related dts file, remove all the root clock setting in board dts file, after this patch, SDR104/HS200 work at 132MHz, DDR50/DDR52 work at 33MHz. Signed-off-by: Haibo Chen Signed-off-by: Arulpandiyan Vadivel Signed-off-by: Srikanth Krishnakar --- arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts | 3 --- arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts | 4 ---- arch/arm/boot/dts/imx6ull.dtsi | 10 ++++++++-- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts index 69323b663a50..934e6f6b8502 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts @@ -12,9 +12,6 @@ pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD0>; - assigned-clock-rates = <0>, <176000000>; cd-gpios = <>; wp-gpios = <>; vmmc-supply = <>; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts index bf8db204017a..4ea3d91e2cb6 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts @@ -13,10 +13,6 @@ pinctrl-0 = <&pinctrl_usdhc2_8bit>; pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <396000000>; - max-frequency = <132000000>; bus-width = <8>; non-removable; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index b48009c1273b..4fbd5e511a0b 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -885,26 +885,32 @@ }; usdhc1: usdhc@02190000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02190000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_USDHC1>, <&clks IMX6UL_CLK_USDHC1>, <&clks IMX6UL_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; bus-width = <4>; fsl,tuning-step= <2>; status = "disabled"; }; usdhc2: usdhc@02194000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02194000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_USDHC2>, <&clks IMX6UL_CLK_USDHC2>, <&clks IMX6UL_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; bus-width = <4>; fsl,tuning-step= <2>; status = "disabled"; -- 2.17.1