From 170da3c5cc13158659fc6aecd81686a5ee11ec26 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 3 May 2017 08:06:47 +0800 Subject: [PATCH] MLK-14695-1 ARM64: dts: freescale: imx8qm: update changes on bring-up Update changes based on i.MX8QM-LPDDR4-ARM2 board bring-up. Signed-off-by: Anson Huang --- arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 287 +++++++++++++++--- 1 file changed, 242 insertions(+), 45 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index cd703d19df0c..2d58f2c50569 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { compatible = "fsl,imx8qm"; @@ -30,8 +31,10 @@ serial0 = &lpuart0; serial1 = &lpuart1; mmc0 = &usdhc1; + mmc1 = &usdhc2; ethernet1 = &fec1; ethernet2 = &fec2; + usbphy0 = &usbphy1; }; memory@80000000 { @@ -49,7 +52,7 @@ linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0 0x08000000>; + size = <0 0x28000000>; alloc-ranges = <0 0x80000000 0 0x80000000>; linux,cma-default; }; @@ -102,6 +105,32 @@ #address-cells = <1>; #size-cells = <0>; + pd_mipi0: PD_MIPI0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi0_i2c0: PD_MIPI0_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + + pd_mipi0_i2c1: PD_MIPI0_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + + pd_mipi0_pwm: PD_MIPI0_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + }; + pd_lvds0: PD_LVDS0 { reg = ; #power-domain-cells = <0>; @@ -115,12 +144,6 @@ power-domains =<&pd_lvds0>; }; - pd_lvds0_i2c1: PD_LVDS0_I2C1 { - reg = ; - #power-domain-cells = <0>; - power-domains =<&pd_lvds0>; - }; - pd_lvds0_pwm: PD_LVDS0_PWM { reg = ; #power-domain-cells = <0>; @@ -135,6 +158,31 @@ #power-domain-cells = <0>; #address-cells = <1>; #size-cells = <0>; + pd_mipi1: PD_MIPI1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi1_i2c0: PD_MIPI1_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + + pd_mipi1_i2c1: PD_MIPI1_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + + pd_mipi1_pwm: PD_MIPI1_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + }; pd_lvds1: PD_LVDS1 { reg = ; @@ -149,12 +197,6 @@ power-domains =<&pd_lvds1>; }; - pd_lvds1_i2c1: PD_LVDS1_I2C1 { - reg = ; - #power-domain-cells = <0>; - power-domains =<&pd_lvds1>; - }; - pd_lvds1_pwm: PD_LVDS1_PWM { reg = ; #power-domain-cells = <0>; @@ -304,6 +346,13 @@ #power-domain-cells = <0>; power-domains = <&pd_conn>; }; + + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usbotg1: PD_CONN_USB_1 { reg = ; #power-domain-cells = <0>; @@ -694,7 +743,7 @@ }; i2c0: i2c@5a800000 { - compatible = "fsl,imx8qm-lpi2c"; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x0 0x5a800000 0x0 0x4000>; interrupts = ; interrupt-parent = <&gic>; @@ -707,7 +756,7 @@ }; i2c1: i2c@5a810000 { - compatible = "fsl,imx8qm-lpi2c"; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x0 0x5a810000 0x0 0x4000>; interrupts = ; interrupt-parent = <&gic>; @@ -715,12 +764,11 @@ clock-names = "per"; assigned-clock-names = <&clk IMX8QM_I2C1_CLK>; assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c1>; status = "disabled"; }; i2c2: i2c@5a820000 { - compatible = "fsl,imx8qm-lpi2c"; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x0 0x5a820000 0x0 0x4000>; interrupts = ; interrupt-parent = <&gic>; @@ -733,7 +781,7 @@ }; i2c3: i2c@5a830000 { - compatible = "fsl,imx8qm-lpi2c"; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x0 0x5a830000 0x0 0x4000>; interrupts = ; interrupt-parent = <&gic>; @@ -746,7 +794,7 @@ }; i2c4: i2c@5a840000 { - compatible = "fsl,imx8qm-lpi2c"; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x0 0x5a840000 0x0 0x4000>; interrupts = ; interrupt-parent = <&gic>; @@ -758,6 +806,34 @@ status = "disabled"; }; + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56247000 0x0 0x1000>; + interrupts = <0 57 4>; + fsl,irq-steer = <0x56240000>; + fsl,irq-num = <0x200>; + clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds0_i2c0>; + status = "disabled"; + }; + + i2c1_lvds1: i2c@57247000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x57247000 0x0 0x1000>; + interrupts = <0 58 4>; + fsl,irq-steer = <0x57240000>; + fsl,irq-num = <0x200>; + clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds1_i2c0>; + status = "disabled"; + }; + imxdpu0: imxdpu0@0x56180000 { compatible = "fsl,imx8qm-imxdpuv1"; reg = <0x0 0x56000000 0x0 0x1000000>; @@ -790,30 +866,73 @@ status = "disabled"; }; + framebuffer0: framebuffer@0 { + compatible = "imxdpuv1-framebuffer"; + reg = <0x0 0x56220000 0x0 0x10000>; + clocks = + <&clk IMX8QM_DC0_PLL0_CLK>, + <&clk IMX8QM_DC0_DISP0_CLK>, + <&clk IMX8QM_MIPI0_PXL_CLK>, + <&clk IMX8QM_MIPI0_BYPASS_CLK>; + clock-names = "clk_pll", "clk_disp", "clk_di", "clk_di_bypass"; + width = <720>; + height = <480>; + stride = <(720*4)>; + format = "b8g8r8a8"; + power-domains = <&pd_mipi0>; + status = "disabled"; + }; + framebuffer1: framebuffer@1 { compatible = "imxdpuv1-framebuffer"; reg = <0x0 0x56240000 0x0 0x10000>; - clocks = <&clk IMX8QM_DC0_PLL1_CLK>, <&clk IMX8QM_DC0_DISP1_CLK>, - <&clk IMX8QM_LVDS0_PIXEL_CLK>; - clock-names = "clk_pll", "clk_disp", "clk_di"; + clocks = + <&clk IMX8QM_DC0_PLL1_CLK>, + <&clk IMX8QM_DC0_DISP1_CLK>, + <&clk IMX8QM_LVDS0_PIXEL_CLK>, + <&clk IMX8QM_LVDS0_BYPASS_CLK>, + <&clk IMX8QM_LVDS0_PHY_CLK>; + clock-names = "clk_pll", "clk_disp", "clk_di", + "clk_di_bypass", "clk_di_phy"; + width = <1920>; + height = <1080>; + stride = <(1920*4)>; + format = "b8g8r8a8"; + power-domains = <&pd_lvds0>; + status = "disabled"; + }; + + framebuffer2: framebuffer@2 { + compatible = "imxdpuv1-framebuffer"; + reg = <0x0 0x57220000 0x0 0x10000>; + clocks = + <&clk IMX8QM_DC1_PLL0_CLK>, + <&clk IMX8QM_DC1_DISP0_CLK>, + <&clk IMX8QM_MIPI1_PXL_CLK>, + <&clk IMX8QM_MIPI1_BYPASS_CLK>; + clock-names = "clk_pll", "clk_disp", "clk_di", "clk_di_bypass"; width = <720>; height = <480>; stride = <(720*4)>; format = "b8g8r8a8"; - power-domains = <&pd_lvds0>; + power-domains = <&pd_mipi1>; status = "disabled"; }; framebuffer3: framebuffer@3 { compatible = "imxdpuv1-framebuffer"; reg = <0x0 0x57240000 0x0 0x10000>; - clocks = <&clk IMX8QM_DC1_PLL1_CLK>, + clocks = + <&clk IMX8QM_DC1_PLL1_CLK>, <&clk IMX8QM_DC1_DISP1_CLK>, - <&clk IMX8QM_LVDS1_PIXEL_CLK>; - clock-names = "clk_pll", "clk_disp", "clk_di"; - width = <720>; - height = <480>; - stride = <(720*4)>; + <&clk IMX8QM_LVDS1_PIXEL_CLK>, + <&clk IMX8QM_LVDS1_BYPASS_CLK>, + <&clk IMX8QM_LVDS1_PHY_CLK>; + clock-names = "clk_pll", "clk_disp", "clk_di", + "clk_di_bypass", "clk_di_phy"; + width = <1920>; + height = <1080>; + stride = <(1920*4)>; format = "b8g8r8a8"; power-domains = <&pd_lvds1>; status = "disabled"; @@ -823,10 +942,14 @@ compatible = "fsl,imx8qm-lvds"; reg = <0x0 0x56241000 0x0 0x1000>; interrupts = <0 57 4>; - clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>, + clocks = + <&clk IMX8QM_LVDS0_PIXEL_CLK>, <&clk IMX8QM_LVDS0_PHY_CLK>; clock-names = "clk_pixel", "clk_phy"; power-domains = <&pd_lvds0>; + instance = <0>; + data-width = <24>; + data-mapping = "jeida"; status = "disabled"; }; @@ -834,10 +957,54 @@ compatible = "fsl,imx8qm-lvds"; reg = <0x0 0x57241000 0x0 0x1000>; interrupts = <0 58 4>; - clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>, + clocks = + <&clk IMX8QM_LVDS1_PIXEL_CLK>, <&clk IMX8QM_LVDS1_PHY_CLK>; clock-names = "clk_pixel", "clk_phy"; power-domains = <&pd_lvds1>; + instance = <1>; + data-width = <24>; + data-mapping = "jeida"; + status = "disabled"; + }; + + mipi0: mipi@56220000 { + compatible = "fsl,imx8qm-mipi_dsi"; + reg = <0x0 0x56220000 0x0 0x10000>; + interrupts = <0 59 4>; + fsl,irq-steer = <0x56220000>; + fsl,irq-num = <0x10000>; + clocks = + <&clk IMX8QM_MIPI0_PXL_CLK>, + <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>; + clock-names = + "clk_pixel","clk_tx_esc", "clk_rx_esc"; + power-domains = <&pd_mipi0>; + instance = <0>; + data_lanes = <4>; + virtual_ch = <0>; + dpi_fmt = <5>; + status = "disabled"; + }; + + mipi1: mipi@57220000 { + compatible = "fsl,imx8qm-mipi_dsi"; + reg = <0x0 0x57220000 0x0 0x10000>; + interrupts = <0 60 4>; + fsl,irq-steer = <0x57220000>; + fsl,irq-num = <0x10000>; + clocks = + <&clk IMX8QM_MIPI1_PXL_CLK>, + <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>; + clock-names = + "clk_pixel", "clk_tx_esc", "clk_rx_esc"; + power-domains = <&pd_mipi1>; + instance = <1>; + data_lanes = <4>; + virtual_ch = <0>; + dpi_fmt = <5>; status = "disabled"; }; @@ -943,7 +1110,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - status = "disabled"; }; gpio1: gpio@5d090000 { @@ -954,7 +1120,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - status = "disabled"; }; gpio2: gpio@5d0a0000 { @@ -965,7 +1130,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - status = "disabled"; }; gpio3: gpio@5d0b0000 { @@ -976,7 +1140,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - status = "disabled"; }; gpio4: gpio@5d0c0000 { @@ -987,7 +1150,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - status = "disabled"; }; gpio5: gpio@5d0d0000 { @@ -998,7 +1160,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - status = "disabled"; }; gpio6: gpio@5d0e0000 { @@ -1009,7 +1170,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - status = "disabled"; }; gpio7: gpio@5d0f0000 { @@ -1020,7 +1180,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - status = "disabled"; }; gpt0: gpt0@5d140000 { @@ -1039,7 +1198,7 @@ clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>; clock-names = "core", "shader"; assigned-clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>; - assigned-clock-rates = <800000000>, <1000000000>; + assigned-clock-rates = <650000000>, <700000000>; fsl,sc_gpu_pid = ; power-domains = <&pd_gpu0>; status = "disabled"; @@ -1052,7 +1211,7 @@ clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>; clock-names = "core", "shader"; assigned-clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>; - assigned-clock-rates = <800000000>, <1000000000>; + assigned-clock-rates = <650000000>, <700000000>; fsl,sc_gpu_pid = ; power-domains = <&pd_gpu1>; status = "disabled"; @@ -1144,6 +1303,33 @@ status = "disabled"; }; + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0d0200 0x0 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x200>; + clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + }; + ddr_pmu0: ddr_pmu@5c020000 { compatible = "fsl,imx8-ddr-pmu"; reg = <0x0 0x5c020000 0x0 0x10000>; @@ -1154,10 +1340,6 @@ reg = <0x0 0x5c120000 0x0 0x10000>; }; - rtc: rtc { - compatible = "fsl,imx8qm-rtc"; - }; - vpu: vpu@2c000000 { compatible = "nxp,imx8qm-vpu", "nxp,imx8x-vpu"; reg = <0x0 0x2c000000 0x0 0x1000000>; @@ -1257,4 +1439,19 @@ power-domains = <&pd_asrc0>; status = "disabled"; }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-flexspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, + <0x0 0x08000000 0x0 0x19ffffff>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = ; + clocks = <&clk IMX8QM_FSPI0_CLK>, + <&clk IMX8QM_FSPI0_CLK>; + assigned-clock-rates = <29000000>,<29000000>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; }; -- 2.17.1