From 166f5ecc2381c012222ac3983c6009ec4270f4f5 Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Mon, 11 Oct 2021 09:37:09 +0200 Subject: [PATCH] arm64: dts: imx8mn-somdevices.dtsi: Add SPI and SPI CAN controller. Signed-off-by: Josep Orga --- .../boot/dts/freescale/imx8mn-somdevices.dtsi | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi index 45914e036d96..00fe08ae0307 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi @@ -68,6 +68,13 @@ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + /* fixed clock dedicated to SPI CAN controller */ + clk20m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; }; &A53_0 { @@ -83,6 +90,45 @@ status = "okay"; }; +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&ecspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2518fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio5>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + microchip,clock-allways-on; + microchip,clock-out-div = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_int>; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -443,12 +489,37 @@ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 //GPIO12 >; }; + + pinctrl_can0_int: can1intgrp { + fsl,pins = < + MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x1c4 + >; + }; + pinctrl_csi: csi_grp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 + MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 + MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 + MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -- 2.17.1