From 133418f2ca39e3c86111770f794ff067ac9d8a93 Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Thu, 16 Nov 2017 18:13:20 +0800 Subject: [PATCH] MLK-16890 arm64: dts: imx8qm/qxp: update enet pin setting enet pins dual voltage pads, bit[0] define the drive strength slection, bit[4:1] are reserved, and bit[6:5] define the pull down and pull up. The patch remove the reserved bits setting and pull up the pin. BuildInfo: - SCFW daf9431c, IMX-MKIMAGE 1c6fc7d8, ATF f2547fb - U-Boot 2017.03-00097-gd7599cf Signed-off-by: Fugang Duan Acked-by: Pandy.gao --- .../dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 56 +++++++++---------- .../boot/dts/freescale/fsl-imx8qm-mek.dts | 52 ++++++++--------- .../dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts | 52 ++++++++--------- .../boot/dts/freescale/fsl-imx8qxp-mek.dts | 52 ++++++++--------- 4 files changed, 106 insertions(+), 106 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 44f09a705c4e..d276c8629c45 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -226,39 +226,39 @@ pinctrl_fec1: fec1grp { fsl,pins = < - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 >; }; pinctrl_fec2: fec2grp { fsl,pins = < - SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000048 - SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000048 - SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048 - SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048 - SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048 - SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048 - SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048 - SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048 - SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048 - SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048 - SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048 - SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048 - SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048 - SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048 + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts index eb8249a343c4..02a67d73626d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts @@ -226,37 +226,37 @@ pinctrl_fec1: fec1grp { fsl,pins = < - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 >; }; pinctrl_fec2: fec2grp { fsl,pins = < - SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048 - SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048 - SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048 - SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048 - SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048 - SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048 - SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048 - SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048 - SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048 - SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048 - SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048 - SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts index 0b9f706b5111..3dc9afcc0a00 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts @@ -191,37 +191,37 @@ pinctrl_fec1: fec1grp { fsl,pins = < - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 >; }; pinctrl_fec2: fec2grp { fsl,pins = < - SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 - SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 - SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 - SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 - SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 - SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 - SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 - SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 - SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 - SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 - SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 - SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000020 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000020 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000020 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000020 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000020 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000020 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts index 86cd096aa168..c3d21e756f89 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts @@ -273,37 +273,37 @@ pinctrl_fec1: fec1grp { fsl,pins = < - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 >; }; pinctrl_fec2: fec2grp { fsl,pins = < - SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 - SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 - SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 - SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 - SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 - SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 - SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 - SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 - SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 - SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 - SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 - SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000020 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000020 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000020 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000020 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000020 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000020 >; }; -- 2.17.1