From 0c8e6e820db628c6a3e6dd42cdc4f2ab1f67b6ed Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Fri, 29 Apr 2016 10:42:47 +0800 Subject: [PATCH] MLK-12731 usb: chipidea: imx: add missing HSIC initialization for imx6qdl/sl This piece of code is existed at imx_3.10, but missing at imx_3.14 and imx_4.1, port it from imx_3.10. Signed-off-by: Peter Chen --- drivers/usb/chipidea/usbmisc_imx.c | 45 +++++++++++++++++------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c index 6e23a327e675..62f45ecbaa54 100644 --- a/drivers/usb/chipidea/usbmisc_imx.c +++ b/drivers/usb/chipidea/usbmisc_imx.c @@ -382,7 +382,7 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data) { struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev); unsigned long flags; - u32 reg; + u32 reg, val; if (data->index > 3) return -EINVAL; @@ -403,6 +403,27 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data) writel(reg | MX6_BM_NON_BURST_SETTING, usbmisc->base + data->index * 4); + /* For HSIC controller */ + if (data->index == 2 || data->index == 3) { + val = readl(usbmisc->base + data->index * 4); + writel(val | MX6_BM_UTMI_ON_CLOCK, + usbmisc->base + data->index * 4); + val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + + (data->index - 2) * 4); + val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON; + writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + + (data->index - 2) * 4); + + /* + * Need to add delay to wait 24M OSC to be stable, + * It is board specific. + */ + regmap_read(data->anatop, ANADIG_ANA_MISC0, &val); + /* 0 <= data->osc_clkgate_delay <= 7 */ + if (data->osc_clkgate_delay > ANADIG_ANA_MISC0_CLK_DELAY(val)) + regmap_write(data->anatop, ANADIG_ANA_MISC0_SET, + (data->osc_clkgate_delay) << 26); + } spin_unlock_irqrestore(&usbmisc->lock, flags); usbmisc_imx6q_set_wakeup(data, false); @@ -419,9 +440,9 @@ static int usbmisc_imx6sx_init(struct imx_usbmisc_data *data) usbmisc_imx6q_init(data); + spin_lock_irqsave(&usbmisc->lock, flags); if (data->index == 0 || data->index == 1) { reg = usbmisc->base + MX6_USB_OTG1_PHY_CTRL + data->index * 4; - spin_lock_irqsave(&usbmisc->lock, flags); /* Set vbus wakeup source as bvalid */ val = readl(reg); writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg); @@ -432,33 +453,17 @@ static int usbmisc_imx6sx_init(struct imx_usbmisc_data *data) val = readl(usbmisc->base + data->index * 4); writel(val & ~MX6SX_BM_DPDM_WAKEUP_EN, usbmisc->base + data->index * 4); - spin_unlock_irqrestore(&usbmisc->lock, flags); } /* For HSIC controller */ if (data->index == 2) { - spin_lock_irqsave(&usbmisc->lock, flags); - val = readl(usbmisc->base + data->index * 4); - writel(val | MX6_BM_UTMI_ON_CLOCK, - usbmisc->base + data->index * 4); val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + (data->index - 2) * 4); - val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON | - MX6SX_BM_HSIC_AUTO_RESUME; + val |= MX6SX_BM_HSIC_AUTO_RESUME; writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + (data->index - 2) * 4); - spin_unlock_irqrestore(&usbmisc->lock, flags); - - /* - * Need to add delay to wait 24M OSC to be stable, - * it's board specific. - */ - regmap_read(data->anatop, ANADIG_ANA_MISC0, &val); - /* 0 <= data->osc_clkgate_delay <= 7 */ - if (data->osc_clkgate_delay > ANADIG_ANA_MISC0_CLK_DELAY(val)) - regmap_write(data->anatop, ANADIG_ANA_MISC0_SET, - (data->osc_clkgate_delay) << 26); } + spin_unlock_irqrestore(&usbmisc->lock, flags); return 0; } -- 2.17.1