From 0acd1d8215f8285ed8dbbb91cbc2d81821d90182 Mon Sep 17 00:00:00 2001 From: Robert Chiras Date: Fri, 8 Dec 2017 13:16:18 +0200 Subject: [PATCH] MLK-17138: arm64: dts: sl-imx8qm.dtsi: Quad display support for 8QM Add DTS files fo quad display on 8QM boards. Currently, there is only one file for this: fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts, which is the combination for 2 LVDS + 2 MIPI-HDMI on LPDDR4 board. This patch adds the other possible use-cases: - 2 LVDS + 2 MIPI-Panel on LPDDR4 - 2 LVDS + 2 MIPI-HDMI on MEK - 2 LVDS + 2 MIPI-Panel on MEK Also: - fix the fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts, since it contained the old mipi_dsi nodes. - fix the order of mipi_dsi nodes in fsl-imx8qm.dtsi, since this order affects the suspend/resume routines. Signed-off-by: Robert Chiras --- arch/arm64/boot/dts/freescale/Makefile | 5 +- .../fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts | 24 ++- .../fsl-imx8qm-lpddr4-arm2-it6263-rm67191.dts | 173 ++++++++++++++++ .../fsl-imx8qm-mek-it6263-adv7535.dts | 187 ++++++++++++++++++ .../fsl-imx8qm-mek-it6263-rm67191.dts | 173 ++++++++++++++++ .../boot/dts/freescale/fsl-imx8qm-mek.dts | 7 + arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 106 +++++----- 7 files changed, 614 insertions(+), 61 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-rm67191.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-it6263-adv7535.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-it6263-rm67191.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 557f0ca970cf..656e20e8ba72 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -14,6 +14,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-mek-dsi-adv7535.dtb \ fsl-imx8qm-mek-dsi-rm67191.dtb \ fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ + fsl-imx8qm-mek-it6263-adv7535.dtb \ + fsl-imx8qm-mek-it6263-rm67191.dtb \ fsl-imx8qm-lpddr4-arm2-dp.dtb \ fsl-imx8qm-lpddr4-arm2-it6263.dtb \ fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dtb \ @@ -24,7 +26,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-lpddr4-arm2-usb3.dtb \ fsl-imx8qm-lpddr4-arm2-dsi-adv7535.dtb \ fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dtb \ - fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dtb + fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dtb \ + fsl-imx8qm-lpddr4-arm2-it6263-rm67191.dtb dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8qxp-mek.dtb \ fsl-imx8qxp-mek-enet2.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts index 8128056761be..8c7c39be53a1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts @@ -14,6 +14,10 @@ #include "fsl-imx8qm-lpddr4-arm2.dts" +&hdmi { + status = "disabled"; +}; + &ldb1_phy { status = "okay"; }; @@ -102,10 +106,6 @@ }; }; -&hdmi { - status = "disabled"; -}; - &i2c0_mipi_dsi0 { #address-cells = <1>; #size-cells = <0>; @@ -122,7 +122,7 @@ port { adv7535_1_in: endpoint { - remote-endpoint = <&mipi_dsi1_out>; + remote-endpoint = <&mipi_dsi_bridge1_adv>; }; }; }; @@ -134,9 +134,13 @@ &mipi_dsi1 { status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; port@1 { - mipi_dsi1_out: endpoint { + mipi_dsi_bridge1_adv: endpoint { remote-endpoint = <&adv7535_1_in>; }; }; @@ -158,7 +162,7 @@ port { adv7535_2_in: endpoint { - remote-endpoint = <&mipi_dsi2_out>; + remote-endpoint = <&mipi_dsi_bridge2_adv>; }; }; }; @@ -170,9 +174,13 @@ &mipi_dsi2 { status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; port@1 { - mipi_dsi2_out: endpoint { + mipi_dsi_bridge2_adv: endpoint { remote-endpoint = <&adv7535_2_in>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-rm67191.dts new file mode 100644 index 000000000000..2564f5b852b8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-rm67191.dts @@ -0,0 +1,173 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&hdmi { + status = "disabled"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@1 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@1 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-it6263-adv7535.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-it6263-adv7535.dts new file mode 100644 index 000000000000..ff1f0ff4992c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-it6263-adv7535.dts @@ -0,0 +1,187 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&hdmi { + status = "disabled"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&i2c0_mipi_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_adv: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; +}; + +&i2c0_mipi_dsi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge2: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_2_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + port@1 { + mipi_dsi_bridge2_adv: endpoint { + remote-endpoint = <&adv7535_2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-it6263-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-it6263-rm67191.dts new file mode 100644 index 000000000000..f347f549da73 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-it6263-rm67191.dts @@ -0,0 +1,173 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&hdmi { + status = "disabled"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@1 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@1 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts index 1f51c69e133f..c114e388a59d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts @@ -533,6 +533,13 @@ >; }; + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + pinctrl_lvds0_pwm0: lvds0pwm0grp { fsl,pins = < SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index 65b758bf5aa7..4f69421dfcfe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -1492,6 +1492,33 @@ status = "disabled"; }; + mipi_dsi1: mipi_dsi@56228000 { + compatible = "fsl,imx8qm-mipi-dsi"; + clocks = + <&clk IMX8QM_MIPI0_PXL_CLK>, + <&clk IMX8QM_MIPI0_BYPASS_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi0>; + csr = <&mipi_dsi_csr1>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + pwr-delay = <100>; + status = "disabled"; + + port@0 { + mipi_dsi1_in: endpoint { + remote-endpoint = <&dpu1_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi1_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_in>; + }; + }; + }; + mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { #address-cells = <1>; #size-cells = <0>; @@ -1519,32 +1546,6 @@ }; }; - mipi_dsi1: mipi_dsi@56228000 { - compatible = "fsl,imx8qm-mipi-dsi"; - clocks = - <&clk IMX8QM_MIPI0_PXL_CLK>, - <&clk IMX8QM_MIPI0_BYPASS_CLK>, - <&clk IMX8QM_CLK_DUMMY>; - clock-names = "pixel", "bypass", "phy_ref"; - power-domains = <&pd_mipi0>; - csr = <&mipi_dsi_csr1>; - phys = <&mipi_dsi_phy1>; - phy-names = "dphy"; - status = "disabled"; - - port@0 { - mipi_dsi1_in: endpoint { - remote-endpoint = <&dpu1_disp0_mipi_dsi>; - }; - }; - - port@1 { - mipi_dsi1_out: endpoint { - remote-endpoint = <&mipi_dsi_bridge1_in>; - }; - }; - }; - lvds_region1: lvds_region@56240000 { compatible = "fsl,imx8qm-lvds-region", "syscon"; reg = <0x0 0x56240000 0x0 0x10000>; @@ -1906,6 +1907,33 @@ status = "disabled"; }; + mipi_dsi2: mipi_dsi@57228000 { + compatible = "fsl,imx8qm-mipi-dsi"; + clocks = + <&clk IMX8QM_MIPI1_PXL_CLK>, + <&clk IMX8QM_MIPI1_BYPASS_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi1>; + csr = <&mipi_dsi_csr2>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + pwr-delay = <100>; + status = "disabled"; + + port@0 { + mipi_dsi2_in: endpoint { + remote-endpoint = <&dpu2_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi2_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_in>; + }; + }; + }; + mipi_dsi_bridge2: mipi_dsi_bridge@57228000 { #address-cells = <1>; #size-cells = <0>; @@ -1933,32 +1961,6 @@ }; }; - mipi_dsi2: mipi_dsi@57228000 { - compatible = "fsl,imx8qm-mipi-dsi"; - clocks = - <&clk IMX8QM_MIPI1_PXL_CLK>, - <&clk IMX8QM_MIPI1_BYPASS_CLK>, - <&clk IMX8QM_CLK_DUMMY>; - clock-names = "pixel", "bypass", "phy_ref"; - power-domains = <&pd_mipi1>; - csr = <&mipi_dsi_csr2>; - phys = <&mipi_dsi_phy2>; - phy-names = "dphy"; - status = "disabled"; - - port@0 { - mipi_dsi2_in: endpoint { - remote-endpoint = <&dpu2_disp0_mipi_dsi>; - }; - }; - - port@1 { - mipi_dsi2_out: endpoint { - remote-endpoint = <&mipi_dsi_bridge2_in>; - }; - }; - }; - lvds_region2: lvds_region@57240000 { compatible = "fsl,imx8qm-lvds-region", "syscon"; reg = <0x0 0x57240000 0x0 0x10000>; -- 2.17.1