From 082e16654b7c5542ad23f80d126257df50f65054 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 21 Jan 2019 00:33:38 -0800 Subject: [PATCH] MLK-20784-2 imx8mm: Load fuse for TMU TCALIV and TASR On iMX8MM, the default value of TMU registers TCALIV and TASR need be loaded from fuse. HW won't do this, it expect SW loads them before using TMU. Signed-off-by: Ye Li Reviewed-by: Bai Ping (cherry picked from commit 9dada8a697b1c103fdb28f528f168da7ecc20849) --- .../include/asm/arch-imx8m/imx-regs-imx8mq.h | 13 +++++++++- arch/arm/mach-imx/imx8m/soc.c | 26 ++++++++++++++++++- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h index 5189e05dfb..c7b910424f 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP */ #ifndef __ASM_ARCH_IMX8MQ_REGS_H__ @@ -216,6 +216,17 @@ struct fuse_bank1_regs { u32 rsvd3[3]; }; +struct fuse_bank3_regs { + u32 mem_trim0; + u32 rsvd0[3]; + u32 mem_trim1; + u32 rsvd1[3]; + u32 ana0; + u32 rsvd2[3]; + u32 ana1; + u32 rsvd3[3]; +}; + struct anamix_pll { u32 audio_pll1_cfg0; u32 audio_pll1_cfg1; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 16bec37e4f..de90710bbf 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * * Peng Fan */ @@ -415,3 +415,27 @@ int imx8m_usb_power(int usb_id, bool on) return 0; } + +void nxp_tmu_arch_init(void *reg_base) +{ + if (is_imx8mm()) { + /* Load TCALIV and TASR from fuses */ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[3]; + struct fuse_bank3_regs *fuse = + (struct fuse_bank3_regs *)bank->fuse_regs; + + u32 tca_rt, tca_hr, tca_en; + u32 buf_vref, buf_slope; + + tca_rt = fuse->ana0 & 0xFF; + tca_hr = (fuse->ana0 & 0xFF00) >> 8; + tca_en = (fuse->ana0 & 0x2000000) >> 25; + + buf_vref = (fuse->ana0 & 0x1F00000) >> 20; + buf_slope = (fuse->ana0 & 0xF0000) >> 16; + + writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28); + writel((tca_en << 31) |(tca_hr <<16) | tca_rt, (ulong)reg_base + 0x30); + } +} -- 2.17.1