From 0676f2b7bfe9b62cc051af26865d81fb31d38483 Mon Sep 17 00:00:00 2001 From: Josep Orga Date: Tue, 10 Jan 2023 18:22:20 +0100 Subject: [PATCH] =?utf8?q?arm64:=20dts:=20Change=20old=20UART4=20pins:=20?= =?utf8?q?=09=C2=B7=20Ethernet=20phy=20reset=20changed=20to=20SAI2=5FMCLK?= =?utf8?q?=5FGPIO4=5FIO27.=20=09=C2=B7=20Pcie=20clkreq=20changed=20to=20I2?= =?utf8?q?C4=5FSCL=5FPCIE1=5FCLKREQ=5FB.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Josep Orga --- arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi index a6d8da980feb..bc19efcd1447 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi @@ -215,7 +215,7 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; - phy-reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; phy-reset-post-delay = <150>; phy-reset-duration = <10>; phy-reset-in-suspend; @@ -751,7 +751,7 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x19 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 >; }; @@ -801,7 +801,7 @@ pinctrl_pcie0: pcie0grp { fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x41 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x41 >; -- 2.17.1