From 02f564238cdb0393d82192ef403c970422fd1481 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 15 Feb 2017 17:34:10 +0800 Subject: [PATCH] MLK-13929-4 mx7ulp: Update registers and memory map for DSI and LCDIF Update the registers base address and LCDIF registers structure for mx7ulp. Signed-off-by: Ye Li (cherry picked from commit 29a2032fc0c2330718dbab1f96c1201ae5b49b6f) (cherry picked from commit d9c18658e20ad8cca6f1d1fda39c2c0b8f4fed95) (cherry picked from commit d7f8f2690ceec70fdaebe91cbd3cc08688ef7543) --- arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 5fc31ffab0..8f15769f1a 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP */ #ifndef _MX7ULP_REGS_H_ @@ -65,6 +66,8 @@ #define SIM1_PCC1_SLOT (48) #define MMDC0_AIPS3_SLOT (43) #define IOMUXC_DDR_AIPS3_SLOT (45) +#define DSI_AIPS3_SLOT (41) +#define LCDIF_AIPS3_SLOT (42) #define LPI2C0_AIPS0_SLOT (51) #define LPI2C1_AIPS0_SLOT (52) @@ -178,6 +181,10 @@ #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) +#define DSI_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * DSI_AIPS3_SLOT))) +#define LCDIF_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LCDIF_AIPS3_SLOT))) +#define MXS_LCDIF_BASE LCDIF_RBASE + #define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) #define SNVS_LP_LPCR (SNVS_BASE + 0x38) @@ -956,6 +963,8 @@ #define SNVS_LPCR_DPEN (0x20) #define SNVS_LPCR_SRTC_ENV (0x1) +#include + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include -- 2.17.1