From 00e65fa6c30426b0b130db4fbdad3328a11e9b16 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 20 Aug 2015 20:25:28 +0800 Subject: [PATCH] MLK-11387-3 ARM: imx: update ddr freq scale setting on imx7d To pass stress test in high temperature environment, according to design team's suggestion, need to adjust ddr phy setting for LPDDR3. Signed-off-by: Anson Huang --- arch/arm/mach-imx/lpddr3_freq_imx.S | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S index 0ced151a01c7..9357627d8c57 100644 --- a/arch/arm/mach-imx/lpddr3_freq_imx.S +++ b/arch/arm/mach-imx/lpddr3_freq_imx.S @@ -15,6 +15,7 @@ #include #include "hardware.h" +#define DDRC_MSTR 0x0 #define DDRC_STAT 0x4 #define DDRC_PWRCTL 0x30 #define DDRC_DBG1 0x304 @@ -36,6 +37,7 @@ #define DDRPHY_OFFSETW_CON0 0x30 #define DDRPHY_OFFSETW_CON1 0x34 #define DDRPHY_OFFSETW_CON2 0x38 +#define DDRPHY_RFSHTMG 0x64 #define DDRPHY_CA_DSKEW_CON0 0x7c #define DDRPHY_CA_DSKEW_CON1 0x80 #define DDRPHY_CA_DSKEW_CON2 0x84 @@ -118,8 +120,22 @@ .macro switch_to_below_100m + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + bne 9f + + /* LPDDR3 */ + ldr r7, =0x00000100 + str r7, [r5, #DDRPHY_PHY_CON1] + b 10f +9: + /* LPDDR2 */ ldr r7, =0x10010100 str r7, [r5, #DDRPHY_PHY_CON1] +10: + ldr r7, =0x00020038 + str r7, [r5, #DDRPHY_RFSHTMG] ldr r6, =24000000 cmp r0, r6 @@ -180,6 +196,9 @@ ldr r7, =0x10210100 str r7, [r5, #DDRPHY_PHY_CON1] + ldr r7, =0x00200038 + str r7, [r5, #DDRPHY_RFSHTMG] + /* dram root set to from dram main, div by 2 */ ldr r7, =0x10000001 ldr r8, =0x9880 -- 2.17.1