From 00955d2815c6cb90a9827237b4ad2cbf00a644d5 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 9 May 2018 13:52:20 +0800 Subject: [PATCH] MLK-18243-14 spi: fspi: init unused LUT to 0 If not initialize unused LUT to 0, the value is random which might cause qspi command failure. On i.MX8QM/QXP, it works ok because ROM inittialize them to 0, but on i.MX8MM, ROM not initialize them, so let's do it here. Signed-off-by: Peng Fan (cherry picked from commit c4bd49c7b249073415f052fb28cd5a4ad374a318) (cherry picked from commit bce752cfe43b3378dbd84b64d46f1d1818e0300f) --- drivers/spi/fsl_fspi.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/spi/fsl_fspi.c b/drivers/spi/fsl_fspi.c index 2009dd0cf4..decd0f7378 100644 --- a/drivers/spi/fsl_fspi.c +++ b/drivers/spi/fsl_fspi.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -192,6 +192,8 @@ static void fspi_set_lut(struct fsl_fspi_priv *priv) fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(0) | PAD0(LUT_PAD1) | INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); /* Write Enable */ lut_base = SEQID_WREN * 4; @@ -317,6 +319,9 @@ static void fspi_set_lut(struct fsl_fspi_priv *priv) PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); #ifdef CONFIG_SPI_FLASH_BAR /* @@ -328,29 +333,47 @@ static void fspi_set_lut(struct fsl_fspi_priv *priv) fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_BRRD) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); lut_base = SEQID_BRWR * 4; fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_BRWR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); lut_base = SEQID_RDEAR * 4; fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_RDEAR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); lut_base = SEQID_WREAR * 4; fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_WREAR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); #endif lut_base = SEQID_RDEVCR * 4; fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_RD_EVCR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); lut_base = SEQID_WREVCR * 4; fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(FSPI_CMD_WR_EVCR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); #ifdef CONFIG_FSPI_QUAD_SUPPORT /* QUAD OUTPUT READ */ @@ -363,6 +386,8 @@ static void fspi_set_lut(struct fsl_fspi_priv *priv) OPRND0(0xc) | PAD0(LUT_PAD4) | INSTR0(LUT_DUMMY_DDR) | OPRND1(0) | PAD1(LUT_PAD4) | INSTR1(LUT_READ_DDR)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); #endif /* Read Flag Status */ -- 2.17.1