From: Liu Ying <victor.liu@nxp.com>
Date: Thu, 14 Nov 2019 07:49:47 +0000 (+0800)
Subject: arm64: imx8qm-ss-lvds.dtsi: Add lvds0/1_pwm_lpcg clocks support
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~577^2~2^2~642
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=ff95a69d044fdd7468646579c537d52773a509cb;p=linux.git

arm64: imx8qm-ss-lvds.dtsi: Add lvds0/1_pwm_lpcg clocks support

This patch adds lvds0/1_pwm_lpcg clocks support for
i.MX8QM LVDS subsystem device tree.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
index 77ec06a441fb..ff54354fbd4c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
@@ -28,6 +28,18 @@
 			power-domains = <&pd IMX_SC_R_LVDS_0>;
 		};
 
+		lvds0_pwm_lpcg: clock-controller@5624300c {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x5624300c 0x4>;
+			#clock-cells = <1>;
+			clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
+				 <&lvds_ipg_clk>;
+			bit-offset = <0 16>;
+			clock-output-names = "lvds0_pwm_lpcg_clk",
+					     "lvds0_pwm_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+		};
+
 		lvds0_i2c0_lpcg: clock-controller@56243010 {
 			compatible = "fsl,imx8qxp-lpcg";
 			reg = <0x56243010 0x4>;
@@ -169,6 +181,18 @@
 			power-domains = <&pd IMX_SC_R_LVDS_1>;
 		};
 
+		lvds1_pwm_lpcg: clock-controller@5724300c {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x5724300c 0x4>;
+			#clock-cells = <1>;
+			clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+				 <&lvds_ipg_clk>;
+			bit-offset = <0 16>;
+			clock-output-names = "lvds1_pwm_lpcg_clk",
+					     "lvds1_pwm_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+		};
+
 		lvds1_i2c0_lpcg: clock-controller@57243010 {
 			compatible = "fsl,imx8qxp-lpcg";
 			reg = <0x57243010 0x4>;