From: Josep Orga <jorga@somdevices.com>
Date: Fri, 13 Aug 2021 10:22:06 +0000 (+0200)
Subject: arm64: dts: imx8mm-somdevices.dtsi: Set proper configuration to usb1 (otg) and add... 
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~32
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=fc177e62ee1a5663ed13c11fcb1e75f4c9539559;p=linux.git

arm64: dts: imx8mm-somdevices.dtsi: Set proper configuration to usb1 (otg) and add usb2 (host).

Signed-off-by: Josep Orga <jorga@somdevices.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
index 2aa4527a2df2..66fa8c96346e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
@@ -59,6 +59,24 @@
 		enable-active-high;
 	};
 
+	reg_usb1: regulator-usb1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus1_regulator";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb2: regulator-usb2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus2_regulator";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	bt_sco_codec: bt_sco_codec {
 		#sound-dai-cells = <1>;
 		compatible = "linux,bt-sco";
@@ -470,13 +488,19 @@
 
 &usbotg1 {
 	dr_mode = "otg";
-	hnp-disable;
-	srp-disable;
-	adp-disable;
-	usb-role-switch;
-	disable-over-current;
-	samsung,picophy-pre-emp-curr-control = <3>;
-	samsung,picophy-dc-vol-level-adjust = <7>;
+	over-current-active-low;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	vbus-supply = <&reg_usb1>;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	over-current-active-low;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg2>;
+	vbus-supply = <&reg_usb2>;
 	status = "okay";
 };
 
@@ -717,6 +741,20 @@
 		>;
 	};
 
+	pinctrl_usbotg1: usbotg1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x16
+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x156
+		>;
+	};
+
+	pinctrl_usbotg2: usbotg2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x16
+			MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC		0x156
+		>;
+	};
+
 	pinctrl_usdhc1_gpio: usdhc1grpgpio {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41