From: Josep Orga <jorga@somdevices.com>
Date: Fri, 13 Aug 2021 10:44:52 +0000 (+0200)
Subject: arm64: dts: imx8mm-somdevices.dtsi: Add SN65DSI83 support and eeprom.
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~29
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=fb0d07298633ca2f4c7f9124dc28d333340d543a;p=linux.git

arm64: dts: imx8mm-somdevices.dtsi: Add SN65DSI83 support and eeprom.

Signed-off-by: Josep Orga <jorga@somdevices.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
index c745a26ad87a..09650903d7d8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
@@ -115,6 +115,14 @@
 		#clock-cells = <0>;
 		clock-frequency = <20000000>;
 	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 2000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
 };
 
 &A53_0 {
@@ -230,6 +238,51 @@
 	pinctrl-0 = <&pinctrl_i2c1>;
 	status = "okay";
 
+	dsi_lvds_bridge: sn65dsi84@2c {
+		compatible = "ti,sn65dsi83";
+		reg = <0x2c>;
+		ti,dsi-lanes = <4>;
+		ti,lvds-format = <2>;
+		ti,lvds-bpp = <24>;
+		ti,lvds-channels = <1>;
+		ti,width-mm = <154>;
+		ti,height-mm = <87>;
+		enable-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds>;
+		status = "okay";
+
+		display-timings {
+			lvds {
+				clock-frequency = <51200000>;
+				hactive = <1024>;
+				vactive = <600>;
+				hfront-porch = <120>;
+				hsync-len = <20>;
+				hback-porch = <140>;
+				vfront-porch = <12>;
+				vsync-len = <3>;
+				vback-porch = <20>;
+
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+
+		port {
+			dsi_lvds_bridge_in: endpoint {
+				remote-endpoint = <&mipi_dsi_out>;
+			};
+		};
+	};
+
+	eeprom@50 {
+		compatible = "microchip,24c02";
+		reg = <0x50>;
+	};
+
 	pmic_nxp: pca9450@25 {
 		compatible = "nxp,pca9450a";
 		reg = <0x25>;
@@ -369,7 +422,7 @@
 };
 
 &lcdif {
-       status = "okay";
+	status = "okay";
 };
 
 &mipi_csi_1 {
@@ -392,13 +445,14 @@
 };
 
 &mipi_dsi {
-       status = "okay";
+	status = "okay";
 
-       port@1 {
-               dsim_to_adv7535: endpoint {
+	port@1 {
+		mipi_dsi_out: endpoint {
+			remote-endpoint = <&dsi_lvds_bridge_in>;
 			attach-bridge;
-               };
-       };
+		};
+	};
 };
 
 &pcie0{
@@ -442,6 +496,12 @@
 	status = "disabled";
 };
 
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
 &resmem {
 	/* global autoconfigured region for contiguous allocations */
 	linux,cma {
@@ -706,6 +766,12 @@
 		>;
 	};
 
+	pinctrl_lvds: lvdsgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x16
+		>;
+	};
+
 	pinctrl_pcie0: pcie0grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B	0x61 /* open drain, pull up */
@@ -720,6 +786,12 @@
 		>;
 	};
 
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x16
+		>;
+	};
+
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41