From: Fancy Fang <chen.fang@nxp.com>
Date: Fri, 15 May 2020 11:08:18 +0000 (+0800)
Subject: MLK-23694-4 arm64: dts: imx8mp: assign 27MHz to mipi_phy1_ref
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~577^2~2^2~412
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=ef9445c379d9650967d18f7a500c144739ebe717;p=linux.git

MLK-23694-4 arm64: dts: imx8mp: assign 27MHz to mipi_phy1_ref

Since the 'mipi_phy1_ref' clock rate is usually set to
be 27MHz and won't be changed after boot up. So assign
27MHz rate instead of 594MHz to this clock is much more
reasonable.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index acf6c725136b..c117f1ad099c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1079,7 +1079,7 @@
 				clock-names = "cfg", "pll-ref";
 				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
 				assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
-				assigned-clock-rates = <594000000>;
+				assigned-clock-rates = <27000000>;
 				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&mipi_phy1_pd>;
 				status = "disabled";