From: Anson Huang Date: Tue, 3 Mar 2020 07:10:20 +0000 (+0800) Subject: arm64: dts: imx8mn: add device nodes support for camera X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~577^2~2^2~508 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=de4b050f45544caa410bad10f0f7bf41fc2feb73;p=linux.git arm64: dts: imx8mn: add device nodes support for camera Camera subsystem of imx8mn is consist of ISI, MIPI CSI and OV5640 sensor, add device nodes for them. Signed-off-by: Guoniu.zhou Signed-off-by: Anson Huang --- diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 432b6070614d..d442b8a0f7e4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -93,6 +93,10 @@ }; }; +&cameradev { + status = "okay"; +}; + &clk { assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; assigned-clock-rates = <393216000>, <361267200>; @@ -224,6 +228,40 @@ AVDD-supply = <®_audio_board>; DVDD-supply = <®_audio_board>; }; + + ov5640_mipi_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; }; &micfil { @@ -235,6 +273,22 @@ status = "okay"; }; +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + mipi1_sensor_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -336,6 +390,19 @@ }; &iomuxc { + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index f133dd56d156..58520192d9b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -38,6 +38,8 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; + isi0 = &isi_0; + csi0 = &mipi_csi_1; }; cpus { @@ -299,6 +301,106 @@ arm,no-tick-in-suspend; }; + isi_resets: isi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + isi-soft-resetn { + compatible = "isi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_ISI_PROC_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_ISI_APB_CLK_RESET>; + }; + + isi-clk-enable { + compatible = "isi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_ISI_PROC_CLK_EN>, + <&dispmix_clk_en IMX8MN_ISI_APB_CLK_EN>; + }; + + }; + + mipi_csi_resets: mipi-csi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + csi-soft-resetn { + compatible = "csi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_MIPI_CSI_PCLK_RESET>, + <&dispmix_sft_rstn IMX8MN_MIPI_CSI_ACLK_RESET>; + }; + + csi-clk-enable { + compatible = "csi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_MIPI_CSI_PCLK_EN>, + <&dispmix_clk_en IMX8MN_MIPI_CSI_ACLK_EN>; + }; + + csi-mipi-reset { + compatible = "csi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_S_RESET>; + }; + }; + + mipi2csi_gasket: gasket@32e28060 { + compatible = "syscon"; + reg = <0x0 0x32e28060 0x0 0x28>; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + isi_0: isi@0x32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x0 0x32e20000 0x0 0x2000>; + power-domains = <&dispmix_pd>; + interrupts = ; + interface = <2 0 2>; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + resets = <&isi_resets>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_1: csi@32e30000 { + compatible = "fsl,imx8mn-mipi-csi"; + reg = <0x0 0x32e30000 0x0 0x10000>; + interrupts = ; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>, <125000000>; + bus-width = <4>; + csi-gpr = <&mipi2csi_gasket>; + power-domains = <&mipi_pd>; + resets = <&mipi_csi_resets>; + status = "disabled"; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>;