From: Josep Orga Date: Wed, 6 Oct 2021 13:17:12 +0000 (+0200) Subject: imx8mn-somdevices: Renamed imx8mn_evk.c -> imx8mn_somdevices.c X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~25 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=dc9fa18f2a29f9f7400a94b68a196fb2b6b27135;p=u-boot.git imx8mn-somdevices: Renamed imx8mn_evk.c -> imx8mn_somdevices.c Signed-off-by: Josep Orga --- diff --git a/board/somdevices/imx8mn_somdevices/imx8mn_evk.c b/board/somdevices/imx8mn_somdevices/imx8mn_evk.c deleted file mode 100644 index 7593761275..0000000000 --- a/board/somdevices/imx8mn_somdevices/imx8mn_evk.c +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/tcpc.h" -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -#ifdef CONFIG_NAND_MXS -#ifdef CONFIG_SPL_BUILD -#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) -#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) -static iomux_v3_cfg_t const gpmi_pads[] = { - IMX8MN_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), - IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), -}; -#endif - -static void setup_gpmi_nand(void) -{ -#ifdef CONFIG_SPL_BUILD - imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); -#endif - - init_nand_clk(); -} -#endif - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - init_uart_clk(1); - -#ifdef CONFIG_NAND_MXS - setup_gpmi_nand(); /* SPL will call the board_early_init_f */ -#endif - - return 0; -} - -#if IS_ENABLED(CONFIG_FEC_MXC) -static int setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - -#ifndef CONFIG_DM_ETH - /* enable rgmii rxc skew and phy mode select to RGMII copper */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); -#endif - - return 0; -} -#endif - -#ifdef CONFIG_USB_TCPC -struct tcpc_port port1; -struct tcpc_port port2; - -static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) -{ - struct udevice *bus; - struct udevice *i2c_dev = NULL; - int ret; - uint8_t valb; - - ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); - if (ret) { - printf("%s: Can't find bus\n", __func__); - return -EINVAL; - } - - ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); - if (ret) { - printf("%s: Can't find device id=0x%x\n", - __func__, addr); - return -ENODEV; - } - - ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); - if (ret) { - printf("%s dm_i2c_read failed, err %d\n", __func__, ret); - return -EIO; - } - valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ - ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); - if (ret) { - printf("%s dm_i2c_write failed, err %d\n", __func__, ret); - return -EIO; - } - - /* Set OVP threshold to 23V */ - valb = 0x6; - ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); - if (ret) { - printf("%s dm_i2c_write failed, err %d\n", __func__, ret); - return -EIO; - } - - return 0; -} - -int pd_switch_snk_enable(struct tcpc_port *port) -{ - if (port == &port1) { - debug("Setup pd switch on port 1\n"); - return setup_pd_switch(1, 0x72); - } else if (port == &port2) { - debug("Setup pd switch on port 2\n"); - return setup_pd_switch(1, 0x73); - } else - return -EINVAL; -} - -struct tcpc_port_config port1_config = { - .i2c_bus = 1, /*i2c2*/ - .addr = 0x50, - .port_type = TYPEC_PORT_UFP, - .max_snk_mv = 5000, - .max_snk_ma = 3000, - .max_snk_mw = 40000, - .op_snk_mv = 9000, - .switch_setup_func = &pd_switch_snk_enable, -}; - -struct tcpc_port_config port2_config = { - .i2c_bus = 1, /*i2c2*/ - .addr = 0x52, - .port_type = TYPEC_PORT_UFP, - .max_snk_mv = 9000, - .max_snk_ma = 3000, - .max_snk_mw = 40000, - .op_snk_mv = 9000, - .switch_setup_func = &pd_switch_snk_enable, -}; - -static int setup_typec(void) -{ - int ret; - - debug("tcpc_init port 2\n"); - ret = tcpc_init(&port2, port2_config, NULL); - if (ret) { - printf("%s: tcpc port2 init failed, err=%d\n", - __func__, ret); - } else if (tcpc_pd_sink_check_charging(&port2)) { - /* Disable PD for USB1, since USB2 has priority */ - port1_config.disable_pd = true; - printf("Power supply on USB2\n"); - } - - debug("tcpc_init port 1\n"); - ret = tcpc_init(&port1, port1_config, NULL); - if (ret) { - printf("%s: tcpc port1 init failed, err=%d\n", - __func__, ret); - } else { - if (!port1_config.disable_pd) - printf("Power supply on USB1\n"); - return ret; - } - - return ret; -} - -int board_usb_init(int index, enum usb_init_type init) -{ - int ret = 0; - struct tcpc_port *port_ptr; - - debug("board_usb_init %d, type %d\n", index, init); - - if (index == 0) - port_ptr = &port1; - else - port_ptr = &port2; - - imx8m_usb_power(index, true); - - if (init == USB_INIT_HOST) - tcpc_setup_dfp_mode(port_ptr); - else - tcpc_setup_ufp_mode(port_ptr); - - return ret; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - int ret = 0; - - debug("board_usb_cleanup %d, type %d\n", index, init); - - if (init == USB_INIT_HOST) { - if (index == 0) - ret = tcpc_disable_src_vbus(&port1); - else - ret = tcpc_disable_src_vbus(&port2); - } - - imx8m_usb_power(index, false); - return ret; -} - -int board_ehci_usb_phy_mode(struct udevice *dev) -{ - int ret = 0; - enum typec_cc_polarity pol; - enum typec_cc_state state; - struct tcpc_port *port_ptr; - - if (dev_seq(dev) == 0) - port_ptr = &port1; - else - port_ptr = &port2; - - tcpc_setup_ufp_mode(port_ptr); - - ret = tcpc_get_cc_status(port_ptr, &pol, &state); - if (!ret) { - if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) - return USB_INIT_HOST; - } - - return USB_INIT_DEVICE; -} - -#endif - -#define DISPMIX 9 -#define MIPI 10 - -int board_init(void) -{ - struct arm_smccc_res res; - -#ifdef CONFIG_USB_TCPC - setup_typec(); -#endif - - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - - arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, - DISPMIX, true, 0, 0, 0, 0, &res); - arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, - MIPI, true, 0, 0, 0, 0, &res); - - return 0; -} - -int board_late_init(void) -{ -#ifdef CONFIG_ENV_IS_IN_MMC - board_late_mmc_env_init(); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "DDR4 EVK"); - env_set("board_rev", "iMX8MN"); -#endif - return 0; -} - -#ifdef CONFIG_ANDROID_SUPPORT -bool is_power_key_pressed(void) { - return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); -} -#endif - -#ifdef CONFIG_FSL_FASTBOOT -#ifdef CONFIG_ANDROID_RECOVERY -int is_recovery_key_pressing(void) -{ - return 0; /* TODO */ -} -#endif /* CONFIG_ANDROID_RECOVERY */ -#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/board/somdevices/imx8mn_somdevices/imx8mn_somdevices.c b/board/somdevices/imx8mn_somdevices/imx8mn_somdevices.c new file mode 100644 index 0000000000..7593761275 --- /dev/null +++ b/board/somdevices/imx8mn_somdevices/imx8mn_somdevices.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS +#ifdef CONFIG_SPL_BUILD +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MN_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; +#endif + +static void setup_gpmi_nand(void) +{ +#ifdef CONFIG_SPL_BUILD + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); +#endif + + init_nand_clk(); +} +#endif + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(1); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + +#ifndef CONFIG_DM_ETH + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else if (port == &port2) { + debug("Setup pd switch on port 2\n"); + return setup_pd_switch(1, 0x73); + } else + return -EINVAL; +} + +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 9000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + /* Disable PD for USB1, since USB2 has priority */ + port1_config.disable_pd = true; + printf("Power supply on USB2\n"); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + if (!port1_config.disable_pd) + printf("Power supply on USB1\n"); + return ret; + } + + return ret; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + struct tcpc_port *port_ptr; + + debug("board_usb_init %d, type %d\n", index, init); + + if (index == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + imx8m_usb_power(index, true); + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + + if (init == USB_INIT_HOST) { + if (index == 0) + ret = tcpc_disable_src_vbus(&port1); + else + ret = tcpc_disable_src_vbus(&port2); + } + + imx8m_usb_power(index, false); + return ret; +} + +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + if (dev_seq(dev) == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} + +#endif + +#define DISPMIX 9 +#define MIPI 10 + +int board_init(void) +{ + struct arm_smccc_res res; + +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + DISPMIX, true, 0, 0, 0, 0, &res); + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + MIPI, true, 0, 0, 0, 0, &res); + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "DDR4 EVK"); + env_set("board_rev", "iMX8MN"); +#endif + return 0; +} + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /* TODO */ +} +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */