From: Josep Orga Date: Fri, 8 Oct 2021 11:56:19 +0000 (+0200) Subject: arm64: dts: imx8mn-somdevices.dtsi: Disabled not used peripherals. X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~18 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=da9bd2265e120d1a008de1be6e8b7c9ba970065c;p=linux.git arm64: dts: imx8mn-somdevices.dtsi: Disabled not used peripherals. Signed-off-by: Josep Orga --- diff --git a/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi index 31659db12a9f..cbd125069dd0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi @@ -65,7 +65,7 @@ }; &cameradev { - status = "okay"; + status = "disabled"; }; &easrc { @@ -98,7 +98,7 @@ &flexspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; + status = "disabled"; }; &gpu { @@ -230,19 +230,19 @@ compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + pinctrl-0 = <&pinctrl_csi>; clocks = <&clk IMX8MN_CLK_CLKO1>; clock-names = "xclk"; assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; assigned-clock-parents = <&clk IMX8MN_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; - powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + //powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + //reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; mclk = <24000000>; mclk_source = <0>; mipi_csi; - status = "okay"; + status = "disabled"; port { ov5640_ep: endpoint { remote-endpoint = <&mipi1_sensor_ep>; @@ -254,10 +254,10 @@ }; &isi_0 { - status = "okay"; + status = "disabled"; cap_device { - status = "okay"; + status = "disabled"; }; }; @@ -278,7 +278,7 @@ &mipi_csi_1 { #address-cells = <1>; #size-cells = <0>; - status = "okay"; + status = "disabled"; port@0 { reg = <0>; mipi1_sensor_ep: endpoint { @@ -404,14 +404,9 @@ }; &iomuxc { - pinctrl_csi_pwn: csi_pwn_grp { + pinctrl_csi: csi_grp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - >; - }; - - pinctrl_csi_rst: csi_rst_grp { - fsl,pins = < MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 >;