From: Josep Orga Date: Thu, 16 Apr 2020 19:30:05 +0000 (+0200) Subject: ARM: imx6ull-somdevices-C0P1.dtsi: X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=cf4c07483cf1aee3690e35f0b524dca418a4ddd5;p=linux.git ARM: imx6ull-somdevices-C0P1.dtsi: · Changed pins to H0.1 version (I2C2, GPIOs, USB1_ID and USBs). · Added EEPROM. · Disable FEC2 with regulator. · Two GPIO-LEDs to control USBs enables. · FEC reset pins must be at SNVS section. · Enable Watchdog. · Remove not used reg_sd1_vmmc. Signed-off-by: Josep Orga --- diff --git a/arch/arm/boot/dts/imx6ull-somdevices.dtsi b/arch/arm/boot/dts/imx6ull-somdevices.dtsi index 5d4c5724c6e5..003d94fe1856 100644 --- a/arch/arm/boot/dts/imx6ull-somdevices.dtsi +++ b/arch/arm/boot/dts/imx6ull-somdevices.dtsi @@ -56,16 +56,19 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - - reg_sd1_vmmc: regulator@1 { +#ifndef DUAL_ETH + reg_fec2_reset: regulator@1 { + //GPIO to disable FEC2 when one ethernet is selected. compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; + regulator-name = "fec2_reset"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; off-on-delay = <20000>; - enable-active-high; + regulator-boot-on; + regulator-always-on; }; +#endif }; leds { @@ -78,14 +81,20 @@ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; -#ifndef DUAL_ETH - led99 { - //GPIO to disable FEC2 when one ethernet is selected. - label = "ethernet_phy_2"; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; + usb1_enable { + //GPIO to enable/disable USB1 + label = "usb_otg1_vbus"; + retain-state-suspended; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + usb2_enable { + //GPIO to enable/disable USB2 + label = "usb_otg2_vbus"; + retain-state-suspended; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; -#endif }; wifi_pwrseq: wifi_pwrseq { @@ -177,10 +186,10 @@ fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ }; -&i2c1 { +&i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; pmic: pf1550@08 { @@ -253,6 +262,11 @@ }; }; }; + + eeprom@50 { + compatible = "microchip,24c02"; + reg = <0x50>; + }; }; &ecspi2 { @@ -282,19 +296,18 @@ pinctrl-0 = <&pinctrl_hog_1>; pinctrl_hog_1: hoggrp-1 { fsl,pins = < - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 //WIFI_IRQ /* SOMDEVICES GPIOs */ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 //GPIO00 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x1b0b0 //GPIO01 - //MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x1b0b0 //GPIO02 - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0 //GPIO03 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b0 //GPIO02 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 //GPIO03 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x1b0b0 //GPIO04 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 //GPIO05 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1b0b0 //GPIO05 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 //GPIO06 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 //GPIO07 - MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0 //GPIO08 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1b0b0 //GPIO08 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x1b0b0 //GPIO09 MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x1b0b0 //GPIO10 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x1b0b0 //GPIO11 @@ -322,7 +335,6 @@ pinctrl_enet1: enet1grp { fsl,pins = < - MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0b0b0//0x70a1 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 @@ -336,7 +348,6 @@ pinctrl_enet2: enet2grp { fsl,pins = < - MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0b0b0//0x70a1 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 @@ -369,9 +380,10 @@ >; }; - pinctrl_i2c1: i2c1grp { + pinctrl_i2c2: i2c2grp { fsl,pins = < - MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 >; }; @@ -456,7 +468,7 @@ pinctrl_usb_otg1_id: usbotg1idgrp { fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 >; }; @@ -551,7 +563,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - //MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; @@ -571,27 +583,33 @@ imx6ul-evk { pinctrl_hog_2: hoggrp-2 { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x80000000 + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 //NAND_nCE2 + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 //NAND_nCE3 + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 //SDIO_WP + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 //USB1_EN + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 //USB2_EN + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 //SDIO_PWR_EN + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0b0 //FEC1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x1b0b0 //FEC2 >; }; pinctrl_wifi_en: pinctrlwifi { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x10071 - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10071 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 //WIFI_EN + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 //WIFI_CHIP_EN >; }; pinctrl_led: ledgrp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 //LED >; }; pinctrl_pf1550: pf1550 { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 //PMIC_INT >; }; }; @@ -675,9 +693,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_otg1_id>; dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; + disable-over-current; status = "okay"; };