From: Josep Orga Date: Tue, 2 Nov 2021 11:21:38 +0000 (+0100) Subject: meta-somdevices: Renamed from imx8mm-somdevices-c0p1 to imx8mmsomdevices. X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=bcfd07485d92e2081151f143f9911ba2d7fe9aac;p=meta-somdevices.git meta-somdevices: Renamed from imx8mm-somdevices-c0p1 to imx8mmsomdevices. Signed-off-by: Josep Orga --- diff --git a/conf/layer.conf b/conf/layer.conf index 3689f3b..acb3c60 100644 --- a/conf/layer.conf +++ b/conf/layer.conf @@ -10,8 +10,8 @@ BBFILE_PATTERN_somdevices = "^${LAYERDIR}/" BBFILE_PRIORITY_somdevices = "9" LAYERSERIES_COMPAT_somdevices = "hardknott" -UBOOT_DTB_NAME_imx8mm-somdevices-c0p1 = "imx8mm-evk.dtb" -KERNEL_DEVICETREE_imx8mm-somdevices-c0p1 = "freescale/imx8mm-somdevices-c0p1.dtb" +UBOOT_DTB_NAME_imx8mmsomdevices = "imx8mm-evk.dtb" +KERNEL_DEVICETREE_imx8mmsomdevices = "freescale/imx8mm-somdevices-c0p1.dtb" # Avoid multiple runtime providers for u-boot-default-env PREFERRED_RPROVIDER_u-boot-default-env ??= "${IMX_DEFAULT_BOOTLOADER}" diff --git a/conf/machine/imx8mm-somdevices-c0p1.conf b/conf/machine/imx8mm-somdevices-c0p1.conf deleted file mode 100644 index 257984a..0000000 --- a/conf/machine/imx8mm-somdevices-c0p1.conf +++ /dev/null @@ -1,40 +0,0 @@ -#@TYPE: Machine -#@NAME: NXP i.MX8MM LPDDR4 SomDevices SMARC -#@SOC: i.MX8MM -#@DESCRIPTION: Machine configuration for SomDevices SMARC imx8mm -#@MAINTAINER: SomDevices - -MACHINEOVERRIDES =. "mx8:mx8m:mx8mm:" - -require conf/machine/include/imx-base.inc -require conf/machine/include/tune-cortexa53.inc - -MACHINE_FEATURES += " pci wifi bluetooth optee" -KERNEL_DEVICETREE = "freescale/imx8mm-somdevices-c0p1.dtb" - -UBOOT_CONFIG ??= "sd" -UBOOT_CONFIG[sd] = "imx8mm_evk_config,sdcard" -UBOOT_CONFIG[fspi] = "imx8mm_evk_fspi_defconfig" -UBOOT_CONFIG[mfgtool] = "imx8mm_evk_config" -SPL_BINARY = "spl/u-boot-spl.bin" - -# Set DDR FIRMWARE -DDR_FIRMWARE_NAME = "lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_dmem.bin" - -# Set u-boot DTB -UBOOT_DTB_NAME = "fsl-imx8mm-evk.dtb" - -# Set imx-mkimage boot target -IMXBOOT_TARGETS = "${@bb.utils.contains('UBOOT_CONFIG', 'fspi', 'flash_evk_flexspi', 'flash_evk', d)}" - -# Set Serial console -SERIAL_CONSOLES = "115200;ttymxc1" - -IMAGE_BOOTLOADER = "imx-boot" - -LOADADDR = "" -UBOOT_SUFFIX = "bin" -UBOOT_MAKE_TARGET = "" -IMX_BOOT_SEEK = "33" - -OPTEE_BIN_EXT = "8mm" diff --git a/conf/machine/imx8mmsomdevices.conf b/conf/machine/imx8mmsomdevices.conf new file mode 100644 index 0000000..257984a --- /dev/null +++ b/conf/machine/imx8mmsomdevices.conf @@ -0,0 +1,40 @@ +#@TYPE: Machine +#@NAME: NXP i.MX8MM LPDDR4 SomDevices SMARC +#@SOC: i.MX8MM +#@DESCRIPTION: Machine configuration for SomDevices SMARC imx8mm +#@MAINTAINER: SomDevices + +MACHINEOVERRIDES =. "mx8:mx8m:mx8mm:" + +require conf/machine/include/imx-base.inc +require conf/machine/include/tune-cortexa53.inc + +MACHINE_FEATURES += " pci wifi bluetooth optee" +KERNEL_DEVICETREE = "freescale/imx8mm-somdevices-c0p1.dtb" + +UBOOT_CONFIG ??= "sd" +UBOOT_CONFIG[sd] = "imx8mm_evk_config,sdcard" +UBOOT_CONFIG[fspi] = "imx8mm_evk_fspi_defconfig" +UBOOT_CONFIG[mfgtool] = "imx8mm_evk_config" +SPL_BINARY = "spl/u-boot-spl.bin" + +# Set DDR FIRMWARE +DDR_FIRMWARE_NAME = "lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_dmem.bin" + +# Set u-boot DTB +UBOOT_DTB_NAME = "fsl-imx8mm-evk.dtb" + +# Set imx-mkimage boot target +IMXBOOT_TARGETS = "${@bb.utils.contains('UBOOT_CONFIG', 'fspi', 'flash_evk_flexspi', 'flash_evk', d)}" + +# Set Serial console +SERIAL_CONSOLES = "115200;ttymxc1" + +IMAGE_BOOTLOADER = "imx-boot" + +LOADADDR = "" +UBOOT_SUFFIX = "bin" +UBOOT_MAKE_TARGET = "" +IMX_BOOT_SEEK = "33" + +OPTEE_BIN_EXT = "8mm" diff --git a/recipes-example/example/example_0.1.bb b/recipes-example/example/example_0.1.bb deleted file mode 100644 index facaae3..0000000 --- a/recipes-example/example/example_0.1.bb +++ /dev/null @@ -1,13 +0,0 @@ -SUMMARY = "bitbake-layers recipe" -DESCRIPTION = "Recipe created by bitbake-layers" -LICENSE = "MIT" - -python do_display_banner() { - bb.plain("***********************************************"); - bb.plain("* *"); - bb.plain("* Example recipe created by bitbake-layers *"); - bb.plain("* *"); - bb.plain("***********************************************"); -} - -addtask display_banner before do_build diff --git a/recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dts b/recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dts index 98e6d17..8e5559c 100644 --- a/recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dts +++ b/recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dts @@ -6,7 +6,7 @@ /dts-v1/; #include -#include "imx8mm-somdevices-c0p1.dtsi" +#include "imx8mm-somdevices.dtsi" / { model = "FSL i.MX8MM µSMARC SOMDEVICES board"; diff --git a/recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dtsi b/recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dtsi deleted file mode 100644 index c4128b6..0000000 --- a/recipes-kernel/linux/files/imx8mm-somdevices-c0p1.dtsi +++ /dev/null @@ -1,1160 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 NXP - */ - -/dts-v1/; - -#include -#include "imx8mm.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir_recv>; - linux,autosuspend-period = <125>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "status"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - modem_reset: modem-reset { - compatible = "gpio-reset"; - reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - reset-delay-us = <2000>; - reset-post-delay-ms = <40>; - #reset-cells = <0>; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_audio_board: regulator-audio-board { - compatible = "regulator-fixed"; - regulator-name = "EXT_PWREN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - startup-delay-us = <300000>; - gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; - regulator-always-on; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <20000>; - enable-active-high; - }; - - bt_sco_codec: bt_sco_codec { - #sound-dai-cells = <1>; - compatible = "linux,bt-sco"; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai1>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&bt_sco_codec 1>; - }; - }; - - /*wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_wlf>; - wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai3>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - }; - };*/ - - /*sound-ak4458 { - compatible = "fsl,imx-audio-ak4458"; - model = "ak4458-audio"; - audio-cpu = <&sai1>; - audio-codec = <&ak4458_1>, <&ak4458_2>; - reset-gpios = <&pca6416 4 GPIO_ACTIVE_HIGH>; - }; - - sound-ak5558 { - compatible = "fsl,imx-audio-ak5558"; - model = "ak5558-audio"; - audio-cpu = <&sai5>; - audio-codec = <&ak5558>; - status = "disabled"; - }; - - sound-ak4497 { - compatible = "fsl,imx-audio-ak4497"; - model = "ak4497-audio"; - audio-cpu = <&sai1>; - audio-codec = <&ak4497>; - status = "disabled"; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif1>; - spdif-out; - spdif-in; - };*/ - - sound-micfil { - compatible = "fsl,imx-audio-micfil"; - model = "imx-audio-micfil"; - cpu-dai = <&micfil>; - }; - - /* fixed clock dedicated to SPI CAN controller */ - clk20m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - }; - -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&csi1_bridge { - fsl,mipi-mode; - status = "okay"; - port { - csi1_ep: endpoint { - remote-endpoint = <&csi1_mipi_ep>; - }; - }; -}; - -&ecspi2 { - #address-cells = <1>; - #size-cells = <0>; - fsl,spi-num-chipselects = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - spidev0: spi@0 { - reg = <0>; - compatible = "rohm,dh2228fv"; - spi-max-frequency = <500000>; - }; -}; - -&ecspi3 { - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; - /* This property is required, even if marked as obsolete in the doku */ - //fsl,spi-num-chipselects = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp2518fd"; - clocks = <&clk20m>; - gpio-controller; - interrupt-parent = <&gpio5>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - microchip,clock-allways-on; - microchip,clock-out-div = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_int>; - reg = <0>; - spi-max-frequency = <2000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - phy-reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - phy-reset-post-delay = <150>; - phy-reset-duration = <10>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - //JOC - //https://github.com/boundarydevices/linux-imx6/tree/boundary-imx_5.10.x_1.0.0-pass1/arch/arm64/boot/dts/freescale - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic_nxp: pca9450@25 { - compatible = "nxp,pca9450a"; - reg = <0x25>; - pinctrl-0 = <&pinctrl_pmic>; - pinctrl-names = "default"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <850000>; - nxp,dvs-standby-voltage = <800000>; - }; - - buck2_reg: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck3_reg: BUCK3 { - regulator-name = "BUCK3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - //https://github.com/karo-electronics/karo-tx-linux/tree/imx_5.10.9_1.0.0/drivers/gpu/drm/bridge/sn65dsi83 - //https://github.com/varigit/linux-imx/blob/5.4-2.1.x-imx_var01/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi - //https://www.digi.com/resources/documentation/digidocs/embedded/dey/2.6/cc8mnano/bsp_r_video-lvds_8mn - dsi_lvds_bridge: sn65dsi84@2c { - compatible = "ti,sn65dsi83"; - reg = <0x2c>; - ti,dsi-lanes = <4>; - ti,lvds-format = <1>; - ti,lvds-bpp = <24>; - ti,lvds-channels = <1>; - ti,width-mm = <154>; - ti,height-mm = <87>; - enable-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds>; - status = "okay"; - - display-timings { - lvds { - /*clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <29>; - vfront-porch = <13>; - hsync-len = <48>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>;*/ - - //clock-frequency = <74200000>; - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <72>; - hsync-len = <80>; - hback-porch = <216>; - vfront-porch = <3>; - vsync-len = <5>; - vback-porch = <22>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - port { - dsi_lvds_bridge_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - /*adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; - reg = <0x3d>; - adi,addr-cec = <0x3b>; - adi,dsi-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - status = "okay"; - - port { - adv7535_from_dsim: endpoint { - remote-endpoint = <&dsim_to_adv7535>; - }; - }; - };*/ - - /*ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 8>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - }; - };*/ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&buck4_reg>; - }; - - /*ak4458_1: ak4458@10 { - compatible = "asahi-kasei,ak4458"; - reg = <0x10>; - AVDD-supply = <®_audio_board>; - DVDD-supply = <®_audio_board>; - }; - - ak4458_2: ak4458@12 { - compatible = "asahi-kasei,ak4458"; - reg = <0x12>; - AVDD-supply = <®_audio_board>; - DVDD-supply = <®_audio_board>; - }; - - ak5558: ak5558@13 { - compatible = "asahi-kasei,ak5558"; - reg = <0x13>; - reset-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; - AVDD-supply = <®_audio_board>; - DVDD-supply = <®_audio_board>; - }; - - ak4497: ak4497@11 { - compatible = "asahi-kasei,ak4497"; - reg = <0x11>; - reset-gpios = <&pca6416 5 GPIO_ACTIVE_HIGH>; - AVDD-supply = <®_audio_board>; - DVDD-supply = <®_audio_board>; - dsd-path = <1>; - };*/ - - ov5640_mipi: ov5640_mipi@3c { - compatible = "ovti,ov5640_mipi"; - reg = <0x3c>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; - clocks = <&clk IMX8MM_CLK_CLKO1>; - clock-names = "csi_mclk"; - assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; - assigned-clock-parents = <&clk IMX8MM_CLK_24M>; - assigned-clock-rates = <24000000>; - csi_id = <0>; - pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - mclk = <24000000>; - mclk_source = <0>; - port { - ov5640_mipi1_ep: endpoint { - remote-endpoint = <&mipi1_sensor_ep>; - }; - }; - }; -}; - -&lcdif { - status = "okay"; -}; - -&mipi_csi_1 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - port { - mipi1_sensor_ep: endpoint@1 { - remote-endpoint = <&ov5640_mipi1_ep>; - data-lanes = <2>; - csis-hs-settle = <13>; - csis-clk-settle = <2>; - csis-wclk; - }; - - csi1_mipi_ep: endpoint@2 { - remote-endpoint = <&csi1_ep>; - }; - }; -}; - -&micfil { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdm>; - assigned-clocks = <&clk IMX8MM_CLK_PDM>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <196608000>; - status = "okay"; -}; - -&mipi_dsi { - status = "okay"; - - port@1 { - mipi_dsi_out: endpoint { - remote-endpoint = <&dsi_lvds_bridge_in>; - attach-bridge; - }; - }; -}; - -&pcie0{ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; - reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, - <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>; - ext_osc = <1>; - status = "disabled"; -}; - -&pcie0_ep{ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, - <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>; - ext_osc = <1>; - status = "disabled"; -}; - -//JOC: TODO check if it is necessary to change sai2 -/*R&sai2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MM_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -};*/ - -&sai1 { - pinctrl-names = "default", "dsd"; - pinctrl-0 = <&pinctrl_sai1>; - pinctrl-1 = <&pinctrl_sai1_dsd>; - assigned-clocks = <&clk IMX8MM_CLK_SAI1>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <49152000>; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, - <&clk IMX8MM_AUDIO_PLL2_OUT>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; - fsl,sai-multi-lane; - fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; - dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; - status = "okay"; -}; - -/*&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -};*/ - -&sai5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai5>; - assigned-clocks = <&clk IMX8MM_CLK_SAI5>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <49152000>; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, - <&clk IMX8MM_AUDIO_PLL2_OUT>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; - fsl,sai-asynchronous; - status = "disabled"; -}; - -&sai6 { - fsl,sai-monitor-spdif; - fsl,sai-asynchronous; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&spdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif1>; - assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, - <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; - clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", - "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; - status = "okay"; -}; - -&uart1 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - fsl,uart-has-rtscts; - resets = <&modem_reset>; - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MM_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - fsl,uart-has-rtscts; - status = "okay"; -}; - -/*&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -};*/ -&usbotg1 { - dr_mode = "otg"; - //over-current-active-low; - pinctrl-names = "default"; - //pinctrl-0 = <&pinctrl_usbotg1>; - //power-active-high; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&vpu_g1 { - status = "okay"; -}; - -&vpu_g2 { - status = "okay"; -}; - -&vpu_h1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&iomuxc { - pinctrl_ir_recv: ir-recv { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f - - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - //MX8MMN(IOMUXC_GPIO1_IO12_USB1_OTG_PWR, 0x16) - //MX8MMN(IOMUXC_GPIO1_IO13_USB1_OTG_OC, 0x156) - MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x16 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x156 - >; - }; - - pinctrl_csi_pwn: csi_pwn_grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - >; - }; - - pinctrl_csi_rst: csi_rst_grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - >; - }; - - pinctrl_ecspi2_cs: ecspi2cs { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 - >; - }; - //JOC - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 /* CAN_SPI_SCK */ - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 /* CAN_SPI_MOSI */ - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 /* CAN_SPI_MISO */ - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 /* CAN_1_SPI_CS */ - >; - }; - - pinctrl_can1_int: can1intgrp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x1c4 /* CAN_1_SPI_INT#_1.8V */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - //MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x19 //JOC - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - /*pinctrl_gpio_wlf: gpiowlfgrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 - >; - };*/ - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch int */ - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_mipi_dsi_en: mipi_dsi_en { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 - >; - }; - - pinctrl_lvds: lvdsgrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 - >; - }; - - pinctrl_pdm: pdmgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 - MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 - MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 - MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 - MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 - MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 - MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 - MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 - MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 - MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 - MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 - MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 - MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 - >; - }; - - pinctrl_sai1_dsd: sai1grp_dsd { - fsl,pins = < - MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 - MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 - MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 - MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 - MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 - MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 - MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 - MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 - MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_sai5: sai5grp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 - MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 - MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 - MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 - MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 - >; - }; - - pinctrl_spdif1: spdif1grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 - MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - /*MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140*/ - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - //MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - //MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 - MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 - MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1grpgpio { - fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { - fsl,pins = < - //MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/recipes-kernel/linux/files/imx8mm-somdevices.dtsi b/recipes-kernel/linux/files/imx8mm-somdevices.dtsi new file mode 100644 index 0000000..c4128b6 --- /dev/null +++ b/recipes-kernel/linux/files/imx8mm-somdevices.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8mm.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + linux,autosuspend-period = <125>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + /*wm8524: audio-codec { + #sound-dai-cells = <0>; + compatible = "wlf,wm8524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_wlf>; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8524-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + simple-audio-card,routing = + "Left Line Out Jack", "LINEVOUTL", + "Right Line Out Jack", "LINEVOUTR"; + + cpudai: simple-audio-card,cpu { + sound-dai = <&sai3>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8524>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + }; + };*/ + + /*sound-ak4458 { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + status = "disabled"; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-ak4497"; + model = "ak4497-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4497>; + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + };*/ + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; + + /* fixed clock dedicated to SPI CAN controller */ + clk20m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&csi1_bridge { + fsl,mipi-mode; + status = "okay"; + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&ecspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + /* This property is required, even if marked as obsolete in the doku */ + //fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2518fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio5>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + microchip,clock-allways-on; + microchip,clock-out-div = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_int>; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + //JOC + //https://github.com/boundarydevices/linux-imx6/tree/boundary-imx_5.10.x_1.0.0-pass1/arch/arm64/boot/dts/freescale + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic_nxp: pca9450@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <850000>; + nxp,dvs-standby-voltage = <800000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + //https://github.com/karo-electronics/karo-tx-linux/tree/imx_5.10.9_1.0.0/drivers/gpu/drm/bridge/sn65dsi83 + //https://github.com/varigit/linux-imx/blob/5.4-2.1.x-imx_var01/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi + //https://www.digi.com/resources/documentation/digidocs/embedded/dey/2.6/cc8mnano/bsp_r_video-lvds_8mn + dsi_lvds_bridge: sn65dsi84@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + ti,dsi-lanes = <4>; + ti,lvds-format = <1>; + ti,lvds-bpp = <24>; + ti,lvds-channels = <1>; + ti,width-mm = <154>; + ti,height-mm = <87>; + enable-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds>; + status = "okay"; + + display-timings { + lvds { + /*clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>;*/ + + //clock-frequency = <74200000>; + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <72>; + hsync-len = <80>; + hback-porch = <216>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <22>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + port { + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /*adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + };*/ + + /*ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + };*/ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + /*ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + reset-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + reset-gpios = <&pca6416 5 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + dsd-path = <1>; + };*/ + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@1 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi1_mipi_ep: endpoint@2 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MM_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + mipi_dsi_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + attach-bridge; + }; + }; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>; + ext_osc = <1>; + status = "disabled"; +}; + +&pcie0_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>; + ext_osc = <1>; + status = "disabled"; +}; + +//JOC: TODO check if it is necessary to change sai2 +/*R&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +};*/ + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +/*&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +};*/ + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "disabled"; +}; + +&sai6 { + fsl,sai-monitor-spdif; + fsl,sai-asynchronous; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/*&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +};*/ +&usbotg1 { + dr_mode = "otg"; + //over-current-active-low; + pinctrl-names = "default"; + //pinctrl-0 = <&pinctrl_usbotg1>; + //power-active-high; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&iomuxc { + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + //MX8MMN(IOMUXC_GPIO1_IO12_USB1_OTG_PWR, 0x16) + //MX8MMN(IOMUXC_GPIO1_IO13_USB1_OTG_OC, 0x156) + MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x16 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x156 + >; + }; + + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + //JOC + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 /* CAN_SPI_SCK */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 /* CAN_SPI_MOSI */ + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 /* CAN_SPI_MISO */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 /* CAN_1_SPI_CS */ + >; + }; + + pinctrl_can1_int: can1intgrp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x1c4 /* CAN_1_SPI_INT#_1.8V */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + //MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x19 //JOC + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + /*pinctrl_gpio_wlf: gpiowlfgrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + };*/ + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch int */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_lvds: lvdsgrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + /*MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140*/ + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + //MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + //MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + //MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/recipes-kernel/linux/linux-imx_%.bbappend b/recipes-kernel/linux/linux-imx_%.bbappend index 1a7e844..2df8dce 100644 --- a/recipes-kernel/linux/linux-imx_%.bbappend +++ b/recipes-kernel/linux/linux-imx_%.bbappend @@ -4,16 +4,16 @@ The kernel is based on the kernel provided by NXP." FILESEXTRAPATHS_prepend := "${THISDIR}/files:" -SRC_URI_append_imx8mm-somdevices-c0p1 += "\ +SRC_URI_append_imx8mmsomdevices += "\ file://imx8mm-somdevices-c0p1.dts \ - file://imx8mm-somdevices-c0p1.dtsi \ + file://imx8mm-somdevices.dtsi \ file://0001-arm64-Add-SomDevices-Smarc-C0P1-to-Makefile.patch \ file://0002-arm64-Add-sn65dsi83-4-support.patch \ file://0003-arm64-Not-to-show-warning-CAN-interface.patch \ " -do_configure_append_imx8mm-somdevices-c0p1 () { +do_configure_append_imx8mmsomdevices () { # For arm64 bit freescale/NXP devices cp ${WORKDIR}/imx8mm-somdevices-c0p1.dts ${S}/arch/arm64/boot/dts/freescale - cp ${WORKDIR}/imx8mm-somdevices-c0p1.dtsi ${S}/arch/arm64/boot/dts/freescale + cp ${WORKDIR}/imx8mm-somdevices.dtsi ${S}/arch/arm64/boot/dts/freescale }