From: Josep Orga <jorga@somdevices.com>
Date: Mon, 11 Oct 2021 07:13:32 +0000 (+0200)
Subject: arm64: dts: imx8mn-somdevices.dtsi: Set proper pins: · Set proper pins to pmic, usdhc... 
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~15
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=b63f69117951c8d17dc962a975d77c02a61e68dc;p=linux.git

arm64: dts: imx8mn-somdevices.dtsi: Set proper pins: · Set proper pins to pmic, usdhc2, mipi_csi, sai5 and uart2. · Added SMARC gpios.

Signed-off-by: Josep Orga <jorga@somdevices.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi
index c6c6e72f9165..a794c2dd64ad 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi
@@ -117,8 +117,8 @@
 		reg = <0x25>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 
 		regulators {
 			buck1: BUCK1{
@@ -390,7 +390,8 @@
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
 	bus-width = <4>;
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 	status = "okay";
@@ -416,10 +417,28 @@
 };
 
 &iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+	pinctrl_hog_1: hoggrp-1 {
+		fsl,pins = <
+			/* SOMDEVICES GPIOs */
+			MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19 //GPIO00
+			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x19 //GPIO01
+			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x19 //GPIO02
+			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x19 //GPIO03
+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19 //GPIO04
+			MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x19 //GPIO05
+			MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1		0x19 //GPIO06
+			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x19 //GPIO07
+			MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29	0x19 //GPIO08
+			MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30	0x19 //GPIO09
+			MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x19 //GPIO10
+			MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19 //GPIO11
+			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x19 //GPIO12
+		>;
+	};
 	pinctrl_csi: csi_grp {
 		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
-			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
 			MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
 		>;
 	};
@@ -498,19 +517,17 @@
 
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
+			MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20	0x141
 		>;
 	};
 
 	pinctrl_sai5: sai5grp {
 		fsl,pins = <
 			MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK	0xd6
-			MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK	0xd6
-			MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC	0xd6
 			MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0	0xd6
-			MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1    0xd6
-			MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2    0xd6
-			MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3    0xd6
+			MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC	0xd6
+			MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK	0xd6
+			MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0	0xd6
 		>;
 	};
 
@@ -532,8 +549,8 @@
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
-			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
+			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
 		>;
 	};
 
@@ -588,7 +605,8 @@
 
 	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
+			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
+			MX8MN_IOMUXC_SD2_WP_GPIO2_IO20	0x1c4
 		>;
 	};