From: Sandor Yu <R01008@freescale.com>
Date: Tue, 17 Nov 2015 09:20:51 +0000 (+0800)
Subject: MLK-11859: dts: Fix imx7D mipi csi reset bit error
X-Git-Tag: C0P2-H0.0--20200415~4036
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=b555657784a6d2e1d93a434984927e954d854f9f;p=linux.git

MLK-11859: dts: Fix imx7D mipi csi reset bit error

There is a error in i.MX7D RM RevB.
Actually the register of SRC_MIPIPHY_RCR(src offset 0x28)
bit 1 for MIPI PHY Master Reset
bit 2 for MIPI PHY Slave Reset.

Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit 4f3128a79c023319c9e21690be866dc46a9d6816)
---

diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index ed0593309472..67348ccae257 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -341,7 +341,7 @@
 				<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
 		clock-names = "mipi_clk", "phy_clk";
 		mipi-phy-supply = <&reg_1p0d>;
-		csis-phy-reset = <&src 0x28 1>;
+		csis-phy-reset = <&src 0x28 2>;
 		bus-width = <4>;
 		status = "disabled";
 	};