From: Liu Ying <victor.liu@nxp.com>
Date: Thu, 14 Nov 2019 08:16:31 +0000 (+0800)
Subject: arm64: imx8qxp-ss-lvds.dtsi: Add pwm_mipi_lvds0/1 support
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~577^2~2^2~639
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=a4b01b05329d6078e82cb8af383c104a91355c98;p=linux.git

arm64: imx8qxp-ss-lvds.dtsi: Add pwm_mipi_lvds0/1 support

This patch adds pwm_mipi_lvds0/1 support for
i.MX8QXP MIPI DSI/LVDS subsystem device tree.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi
index f75d2584e000..86668c1692c7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi
@@ -165,6 +165,20 @@
 			};
 		};
 
+		pwm_mipi_lvds0: pwm@56224000 {
+			compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+			reg = <0x56224000 0x1000>;
+			clocks = <&mipi0_pwm_lpcg 0>,
+				 <&mipi0_pwm_lpcg 1>,
+				 <&mipi0_pwm_lpcg 2>;
+			clock-names = "per", "ipg", "32k";
+			assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-rates = <24000000>;
+			#pwm-cells = <2>;
+			power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+			status = "disabled";
+		};
+
 		i2c0_mipi_lvds0: i2c@56226000 {
 			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 			reg = <0x56226000 0x4000>;
@@ -254,6 +268,20 @@
 			};
 		};
 
+		pwm_mipi_lvds1: pwm@56244000 {
+			compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+			reg = <0x56244000 0x1000>;
+			clocks = <&mipi1_pwm_lpcg 0>,
+				 <&mipi1_pwm_lpcg 1>,
+				 <&mipi1_pwm_lpcg 2>;
+			clock-names = "per", "ipg", "32k";
+			assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-rates = <24000000>;
+			#pwm-cells = <2>;
+			power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+			status = "disabled";
+		};
+
 		i2c0_mipi_lvds1: i2c@56246000 {
 			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 			reg = <0x56246000 0x4000>;