From: Haibo Chen Date: Fri, 15 Nov 2019 12:18:07 +0000 (+0800) Subject: MLK-20420 ARM: dts: imx7ulp-evk: add delay cell for DDR50/DDR52 mode X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~577^2~2^2~628 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=93b853b81a79310505254c269e6c94c2a70a3206;p=linux.git MLK-20420 ARM: dts: imx7ulp-evk: add delay cell for DDR50/DDR52 mode We find some imx7ulp evk board, SD card work in DDR50 mode will meet data CRC error. Only some board has this issue. And eMMC DDR50 mode also has this issue on these boards. For DDR50, do tuning can fix this issue, but eMMC DDR52 do not support tuning. So this patch manually add the delay cell on the fixed clock (FBCLK_SEL = 0). Currently, add 15 delay cell, which can make DDR50/DDR52 works stable on all imx7ulp evk board. Signed-off-by: Haibo Chen Reviewed-by: Dong Aisheng (cherry picked from commit ef369313de747251ff11c108e7fd5bf2b92df603) Signed-off-by: Haibo Chen --- diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 2d3912005b51..8495391f240d 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -417,6 +417,7 @@ pinctrl-1 = <&pinctrl_usdhc0>; pinctrl-2 = <&pinctrl_usdhc0>; pinctrl-3 = <&pinctrl_usdhc0>; + fsl,delay-line = <15>; cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; vmmc-supply = <®_vsd_3v3>; vqmmc-supply = <&vldo2_reg>;