From: Wen He Date: Mon, 12 Aug 2019 10:02:24 +0000 (+0800) Subject: arm64: dts: ls1028a: Add properties node for Display output pixel clock X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~3890^2~14^2~8 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=81f36887ea337b59c12d179eda8f7ea4398bac0e;p=linux.git arm64: dts: ls1028a: Add properties node for Display output pixel clock The LS1028A has a clock domain PXLCLK0 used for the Display output interface in the display core, independent of the system bus frequency, for flexible clock design. This display core has its own pixel clock. This patch enable the pixel clock provider on the LS1028A. Signed-off-by: Wen He Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 5c7a1739daf0..0b317eba746f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -72,11 +72,18 @@ clock-output-names = "sysclk"; }; - dpclk: clock-dp { + osc_27m: clock-osc-27m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; - clock-output-names= "dpclk"; + clock-output-names = "phy_27m"; + }; + + dpclk: clock-controller@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <1>; + clocks = <&osc_27m>; }; aclk: clock-axi { @@ -639,7 +646,7 @@ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, <0 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "DE", "SE"; - clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>; + clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; arm,malidp-arqos-value = <0xd000d000>;