From: Sandor Yu Date: Tue, 20 Apr 2021 03:27:15 +0000 (+0800) Subject: MLK-25454-1 dts: iMX8MP_DDR4: Set LCDIF/HDMI AXI clock rate to nominal mode X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~169 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=81a50fa590d5949505c34c68a8ff6f323514e176;p=linux.git MLK-25454-1 dts: iMX8MP_DDR4: Set LCDIF/HDMI AXI clock rate to nominal mode According IMX8MPIEC, both LCIDF and HDMI AXI clock rate should set to nominal mode for iMX8MP DDR4 board. Clock root Nominal mode Overdrive mode Unit MEDIA_AXI_CLK_ROOT 400 500 MHz HDMI_AXI_CLK_ROOT 400 500 MHz Signed-off-by: Sandor Yu Reviewed-by: Jacky Bai (cherry picked from commit 4e698891f8d8c6bf6a3f6bf870bef1bb603dcddd) --- diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts index 54122d6d4344..25988f054a30 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts @@ -99,7 +99,32 @@ assigned-clock-rates = <400000000>, <600000000>; }; +&lcdif1 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <400000000>, <200000000>; +}; + +&lcdif2 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <400000000>, <200000000>; +}; + &lcdif3 { + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <400000000>, <133000000>; thres-low = <2 3>; /* (FIFO * 2 / 3) */ thres-high = <3 3>; /* (FIFO * 3 / 3) */ status = "okay";