From: Haibo Chen Date: Fri, 29 Nov 2019 08:57:52 +0000 (+0800) Subject: LF-270 ARM64: dts: imx8mq.dtsi: set the IMX8MQ_CLK_NAND_USDHC_BUS clock rate X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~577^2~2^2~584 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=7668662a9a2eca9ed34215f03763348f418eabc4;p=linux.git LF-270 ARM64: dts: imx8mq.dtsi: set the IMX8MQ_CLK_NAND_USDHC_BUS clock rate Need to set the IMX8MQ_CLK_NAND_USDHC_BUS clock rate to 266MHz, to make clock align, otherwise USDHC oparation will has issue. Signed-off-by: Haibo Chen --- diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 4bd8bfcdcac8..fc2600fd880e 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -640,11 +640,13 @@ "clk_ext3", "clk_ext4"; assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, <&clk IMX8MQ_CLK_A53_CORE>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_NOC>; - assigned-clock-rates = <0>, <0>, + assigned-clock-rates = <0>, <0>, <0>, <800000000>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_ARM_PLL_OUT>; + <&clk IMX8MQ_ARM_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>; }; src: reset-controller@30390000 {