From: Ye Li Date: Tue, 3 Apr 2018 07:27:48 +0000 (-0700) Subject: MLK-18152-5 mx6sxsabreauto: Update board codes to align with v2019.04 X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~576 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=72c4c03de0f1cfe55603d712eb068ecfa58d2c2c;p=u-boot.git MLK-18152-5 mx6sxsabreauto: Update board codes to align with v2019.04 Update DM PMIC settings and LDO bypass support. Add BMODE support. Add LVDS and LCD splash screen support Add two ethernet controller support Update environment settings Add plugin support Signed-off-by: Ye Li (cherry picked from commit beaea14e18f138249521f0de8a8ef902d555cb89) (cherry picked from commit c766595b0be6676b57886114f383b2d1c529ce29) (cherry picked from commit e035f2c4746ed35fa39bc9d11d70ff329c1e37fd) --- diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig index ae2ea02439..5e9c06cde0 100644 --- a/board/freescale/mx6sxsabreauto/Kconfig +++ b/board/freescale/mx6sxsabreauto/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sxsabreauto" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg index 4a0bcc5f7d..865f111d26 100644 --- a/board/freescale/mx6sxsabreauto/imximage.cfg +++ b/board/freescale/mx6sxsabreauto/imximage.cfg @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. */ #define __ASSEMBLY__ @@ -15,7 +15,22 @@ IMAGE_VERSION 2 * spi/sd/nand/onenand, qspi/nor */ +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sxsabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif /* * Device Configuration Data (DCD) @@ -133,3 +148,4 @@ DATA 4 0x021b0818 0x00022227 DATA 4 0x021b0004 0x0002556d DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 +#endif diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 7340a34402..9b83d17857 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 nxp * * Author: Ye Li */ @@ -30,6 +31,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +54,13 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SRE_FAST) #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -64,23 +73,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -88,27 +80,28 @@ static void setup_iomux_uart(void) static int setup_fec(void) { + int ret; struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - - return enable_fec_anatop_clock(1, ENET_125MHZ); -} + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); -int board_eth_init(struct bd_info *bis) -{ - int ret; + /* Use 125M anatop REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - setup_fec(); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) { + printf("enable fec0 clock failed\n"); + return ret; + } - ret = fecmxc_initialize_multi(bis, 1, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC%d MXC: %s:failed\n", 1, __func__); + ret = enable_fec_anatop_clock(1, ENET_125MHZ); + if (ret) { + printf("enable fec0 clock failed\n"); + return ret; + } - return ret; + return 0; } int board_phy_config(struct phy_device *phydev) @@ -134,51 +127,64 @@ int power_init_board(void) { struct udevice *dev; int ret; - u32 dev_id, rev_id, i; - u32 switch_num = 6; - u32 offset = PFUZE100_SW1CMODE; - ret = pmic_get("pfuze100", &dev); - if (ret == -ENODEV) - return 0; + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; - if (ret != 0) + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) return ret; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + /* set SW1C staby volatage 1.10V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + /* Enable power of VGEN5 3V3, needed for SD3 */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, LDO_VOL_MASK, (LDOB_3_30V | (1 << LDO_EN))); - /* Init mode to APS_PFM */ - pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + return 0; +} - for (i = 0; i < switch_num - 1; i++) - pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; - /* set SW1AB staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } - /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.15V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, SW1x_1_150V); - /* set SW1C staby volatage 1.10V */ - pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); + /* decrease VDDSOC to 1.15V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, SW1x_1_150V); - /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + set_anatop_bypass(1); - return 0; + printf("switch to ldo_bypass mode!\n"); + } } +#endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { /* OGT1 */ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), /* OTG2 */ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) }; @@ -213,6 +219,7 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif int board_early_init_f(void) { @@ -221,6 +228,136 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lvds_ctrl_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_lvds(struct display_info_t const *dev) +{ + struct gpio_desc desc; + int ret; + + enable_lcdif_clock(dev->bus, 1); + enable_lvds_bridge(dev->bus); + + imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, + ARRAY_SIZE(lvds_ctrl_pads)); + + /* LVDS Enable pin */ + ret = dm_gpio_lookup_name("gpio@30_7", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lvds_en"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); + + /* Set Brightness to high */ + ret = dm_gpio_lookup_name("GPIO6_3", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lcd backlight"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + struct gpio_desc desc; + int ret; + + enable_lcdif_clock(dev->bus, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Power up the LCD */ + ret = dm_gpio_lookup_name("GPIO3_27", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lcd reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +struct display_info_t const displays[] = {{ + .bus = LCDIF2_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .detect = NULL, + .enable = do_enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6SX_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "Boundary-LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + #ifdef CONFIG_FSL_QSPI int board_qspi_init(void) { @@ -300,8 +437,10 @@ int board_init(void) dm_gpio_set_value(&desc, 0); #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); #endif +#endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); @@ -311,6 +450,11 @@ int board_init(void) setup_gpmi_nand(); #endif + /* Also used for OF_CONTROL enabled */ +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return 0; } @@ -330,6 +474,14 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + /* set WDOG_B to reset whole system */ + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } diff --git a/board/freescale/mx6sxsabreauto/plugin.S b/board/freescale/mx6sxsabreauto/plugin.S new file mode 100644 index 0000000000..606bb03cde --- /dev/null +++ b/board/freescale/mx6sxsabreauto/plugin.S @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_sabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x002C003D + str r2, [r0, #0x80c] + ldr r2, =0x00110046 + str r2, [r0, #0x810] + ldr r2, =0x4160016C + str r2, [r0, #0x83c] + ldr r2, =0x013C016C + str r2, [r0, #0x840] + ldr r2, =0x46424446 + str r2, [r0, #0x848] + ldr r2, =0x3A3C3C3A + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000007f + str r2, [r0, #0x040] + ldr r2, =0x85190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00022227 + str r2, [r0, #0x818] + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6sx_sabreauto_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 787b4a70e8..c478f12851 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -13,23 +13,93 @@ #define CONFIG_DBG_MONITOR /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) #define CONFIG_MXC_UART_BASE UART1_BASE +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#ifdef CONFIG_IMX_BOOTAUX + +/* Set to QSPI1 B flash at default */ +#ifdef CONFIG_DM_SPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 +#define SF_QSPI1_B_CS_NUM 2 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x62000000 +#define SF_QSPI1_B_CS_NUM 1 +#endif + + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=Hannstar-XGA\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=6 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ + CONFIG_MFG_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=imx6sx-sabreauto.dtb\0" \ - "fdt_addr=0x88000000\0" \ + "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "panel=Hannstar-XGA\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ @@ -90,6 +160,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif /* Miscellaneous configurable options */ @@ -120,18 +191,13 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT /* DMA stuff, needed for GPMI/MXS NAND support */ /* Network */ - -#define CONFIG_FEC_MXC - -#define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 - +#define CONFIG_ETHPRIME "eth1" #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -141,5 +207,38 @@ #endif #define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_CONSOLE_BG_COL 0x00 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0 +#ifdef CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_CSI +#define CONFIG_VIDEO_PXP +#define CONFIG_VIDEO_VADC +#endif +#endif #endif /* __CONFIG_H */