From: Ye Li <ye.li@nxp.com>
Date: Fri, 15 Dec 2017 07:28:06 +0000 (-0600)
Subject: MLK-17292 mx7ulp: Set A7 core frequency to 500Mhz for B0 chip
X-Git-Tag: rel_imx_4.9.88_2.0.0_ga~112
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=4f822410518cd5847f8621d66c3e3b2599145b9e;p=u-boot.git

MLK-17292 mx7ulp: Set A7 core frequency to 500Mhz for B0 chip

The normal target frequency for ULP A7 core is 500Mhz, but now ROM
set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>
---

diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c
index 4db35e7c7c..98d40d6c1d 100644
--- a/arch/arm/cpu/armv7/mx7ulp/clock.c
+++ b/arch/arm/cpu/armv7/mx7ulp/clock.c
@@ -302,6 +302,8 @@ void clock_init(void)
 
 	scg_a7_soscdiv_init();
 
+	scg_a7_init_core_clk();
+
 	/* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
 	scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
 	scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c
index 6eadd488f4..ce731eb39b 100644
--- a/arch/arm/cpu/armv7/mx7ulp/scg.c
+++ b/arch/arm/cpu/armv7/mx7ulp/scg.c
@@ -1095,3 +1095,39 @@ void scg_a7_info(void)
 	debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));
 	debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));
 }
+
+void scg_a7_init_core_clk(void)
+{
+	u32 val = 0;
+
+	/* The normal target frequency for ULP B0 is 500Mhz, but ROM set it to 413Mhz, need to change SPLL PFD0 FRAC */
+	if (soc_rev() >= CHIP_REV_2_0) {
+
+		/* Switch RCCR SCG to SOSC, firstly check the SOSC is valid */
+		if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) {
+			val = readl(&scg1_regs->rccr);
+			val &= (~SCG_CCR_SCS_MASK);
+			val |= ((SCG_SCS_SYS_OSC) << SCG_CCR_SCS_SHIFT);
+			writel(val, &scg1_regs->rccr);
+
+			/* Swith the PLLS to SPLL clk */
+			val = readl(&scg1_regs->spllcfg);
+			val &= ~SCG_PLL_CFG_PLLSEL_MASK;
+			writel(val, &scg1_regs->spllcfg);
+
+			/* Re-configure PFD0 to 19, A7 SPLL(528MHz) * 18 / 19 = 500MHz */
+			scg_enable_pll_pfd(SCG_SPLL_PFD0_CLK, 19);
+
+			/* Swith the PLLS to SPLL PFD0 */
+			val = readl(&scg1_regs->spllcfg);
+			val |= SCG_PLL_CFG_PLLSEL_MASK;
+			writel(val, &scg1_regs->spllcfg);
+
+			/* Set RCCR SCG to SPLL clk out */
+			val = readl(&scg1_regs->rccr);
+			val &= (~SCG_CCR_SCS_MASK);
+			val |= ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT);
+			writel(val, &scg1_regs->rccr);
+		}
+	}
+}
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h
index 06a6e9f4f9..f46e52baba 100644
--- a/arch/arm/include/asm/arch-mx7ulp/scg.h
+++ b/arch/arm/include/asm/arch-mx7ulp/scg.h
@@ -338,5 +338,6 @@ void scg_a7_nicclk_init(void);
 void scg_a7_sys_clk_sel(enum scg_sys_src clk);
 void scg_a7_info(void);
 void scg_a7_soscdiv_init(void);
+void scg_a7_init_core_clk(void);
 
 #endif