From: Anson Huang Date: Thu, 19 Dec 2019 06:29:53 +0000 (+0800) Subject: MLK-23131-1 arm64: dts: imx8mm/imx8mn: Add dram_pll_div clock for busfreq X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~577^2~2^2~474 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=4f439ebbc4728462cc3e7c4dd51293b129a45a74;p=linux.git MLK-23131-1 arm64: dts: imx8mm/imx8mn: Add dram_pll_div clock for busfreq On i.MX8MM/i.MX8MN platforms, need to add dram_pll_div clock for busfreq driver to update dram_core clock when DRAM frequency switches between low bus mode and high bus mode. Signed-off-by: Anson Huang Reviewed-by: Robin Gong --- diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index a1603e7c55ad..9cd1a9e5e140 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -383,11 +383,12 @@ <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC>, <&clk IMX8MM_CLK_AHB>, <&clk IMX8MM_CLK_MAIN_AXI>, - <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>; + <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_DRAM_PLL>; clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", - "sys_pll1_800m"; + "sys_pll1_800m", "dram_pll_div"; interrupts = , , , ; interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index d06b251632f5..145b5196fb7e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -212,11 +212,12 @@ <&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>, <&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>, <&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>, - <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>; + <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_DRAM_PLL>; clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", - "sys_pll1_800m"; + "sys_pll1_800m", "dram_pll_div"; }; power-domains {