From: Li Jun <jun.li@nxp.com>
Date: Mon, 19 Apr 2021 06:58:44 +0000 (+0800)
Subject: LF-3753 arm64: dts: imx8mp-ddr4-evk: change hsio to be 400M
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~165
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=48d1aa890ae1e3f05623a2c4f8d07b269c0cf7b1;p=linux.git

LF-3753 arm64: dts: imx8mp-ddr4-evk: change hsio to be 400M

Change hsio clock to be 400M(Nominal mode) for ddr4 board.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts
index 25988f054a30..f3eab70e3de0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts
@@ -76,6 +76,34 @@
 	assigned-clock-rates = <800000000>, <800000000>, <300000000>;
 };
 
+&pcie{
+	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+			  <&clk IMX8MP_CLK_PCIE_AUX>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+				 <&clk IMX8MP_SYS_PLL2_50M>;
+	assigned-clock-rates = <400000000>, <10000000>;
+};
+
+&pcie_ep{
+	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+			  <&clk IMX8MP_CLK_PCIE_AUX>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+				 <&clk IMX8MP_SYS_PLL2_50M>;
+	assigned-clock-rates = <400000000>, <10000000>;
+};
+
+&usb_dwc3_0 {
+	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+	assigned-clock-rates = <400000000>;
+};
+
+&usb_dwc3_1 {
+	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+	assigned-clock-rates = <400000000>;
+};
+
 &usdhc3 {
 	status = "disabled";
 };