From: Ye Li <ye.li@nxp.com>
Date: Tue, 13 Aug 2019 10:34:57 +0000 (-0700)
Subject: MLK-22437-1 spi: fsl_qspi: Enable DDR mode on iMX7ULP
X-Git-Tag: rel_imx_4.19.35_1.1.0~78
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=473cc13e29452e152add683d1b3772fb0e7685be;p=u-boot.git

MLK-22437-1 spi: fsl_qspi: Enable DDR mode on iMX7ULP

On iMX7ULP A0, PCC divider for QSPI has timing issue and it is
only possible to use the divider ratio equal to 1 (PCD=0).
This timing issue causes page program working abnormal if DDR_EN
is set. So current QSPI driver has disabled DDR mode on iMX7ULP

Since iMX7ULP B0 has fixed the issue, so re-enable the DDR mode
for iMX7ULP.

Signed-off-by: Ye Li <ye.li@nxp.com>
---

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index f60b4eb806..547c030062 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -431,7 +431,6 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 }
 
-#ifndef CONFIG_MX7ULP
 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 {
 	u32 reg, reg2;
@@ -460,7 +459,6 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 	reg |= BIT(16);
 	qspi_write32(priv->flags, &regs->flshcr, reg);
 }
-#endif
 
 /*
  * There are two different ways to read out the data from the flash:
@@ -503,10 +501,8 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 	qspi_write32(priv->flags, &regs->bfgencr,
 		     SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 
-#ifndef CONFIG_MX7ULP
 	/*Enable DDR Mode*/
 	qspi_enable_ddr_mode(priv);
-#endif
 }
 #endif