From: Josep Orga <jorga@somdevices.com>
Date: Wed, 5 Oct 2022 16:06:02 +0000 (+0200)
Subject: arm64: dts: Enable PCIe and set PCIe reference clock as internal PLL.
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0^0
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=3d53365fd68e52ec70dcf814b4dc7ff6204d6cbb;p=linux.git

arm64: dts: Enable PCIe and set PCIe reference clock as internal PLL.

Signed-off-by: Josep Orga <jorga@somdevices.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
index f33576d0333e..3eaaf86738b4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
@@ -480,8 +480,8 @@
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 				 <&clk IMX8MM_SYS_PLL2_100M>,
 				 <&clk IMX8MM_SYS_PLL2_250M>;
-	ext_osc = <1>;
-	status = "disabled";
+	ext_osc = <0>;
+	status = "okay";
 };
 
 &pcie0_ep{
@@ -499,7 +499,7 @@
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 				 <&clk IMX8MM_SYS_PLL2_100M>,
 				 <&clk IMX8MM_SYS_PLL2_250M>;
-	ext_osc = <1>;
+	ext_osc = <0>;
 	l1ss-disabled;
 	status = "disabled";
 };